Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Public
Document Table of Contents

6.5.4.1. Assigning Input Delay to LVDS Receiver Using Timing Analyzer

To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver from the Timing Analyzer constraints menu.

  1. On the menu in the Timing Analyzer, select Constraints > Set Input Delay.
  2. In the Set Input Delay window, select the desired clock using the pull-down menu. The clock name must reference the source synchronous clock that feeds the LVDS receiver.
  3. Click the Browse button (next to the Targets field).
  4. In the Name Finder window, click List to view a list of all available ports. Select the LVDS receiver serial input ports according to the input delay you set, and click OK.
  5. In the Set Input Delay window, set the appropriate values in the Input delay options and Delay value fields.
  6. Click Run to incorporate these values in the Timing Analyzer.
  7. Repeat from 1 to assign the appropriate delay for all the LVDS receiver input ports. If you have already assigned Input Delay and you need to add more delay to that input port, turn on the Add Delay option.