Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/29/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Device Family Pin Connection Guidelines x
Intel® Stratix® 10 Core Pins Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Intel® Stratix® 10 E-Tile Pins Intel® Stratix® 10 P-Tile Pins Intel® Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins 3.3V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Intel® Stratix® 10 HBM Power Supply Pins Notes to Intel® Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins x
Intel® Stratix® 10 E-Tile Pins Notes to Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins x
Intel® Stratix® 10 P-Tile Power Supply Pins Intel® Stratix® 10 P-Tile Transceiver Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Intel® Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices x
Example 1— Intel® Stratix® 10 GX Example 2— Intel® Stratix® 10 GX Example 3— Intel® Stratix® 10 GX (only for the HF35 Package) Example 4— Intel® Stratix® 10 GX (only for the HF35 Package) Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Intel® Stratix® 10 SX (–2L and –3X parts) Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Intel® Stratix® 10 SX (–2L and –3X parts) Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Intel® Stratix® 10 MX (E-Tile) Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Intel® Stratix® 10 TX (–2L and –3X parts) Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Intel® Stratix® 10 GX 10M Example 20— Intel® Stratix® 10 GX 10M
Intel® Stratix® 10 Device Family Pin Connection Guidelines

Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines

Document Version Changes
2023.12.29
  • Updated the connection guidelines of the VCCIO([2][A,B,C,F,L,M,N], [3][A,B,C,I,J,K,L]) pins.
  • Updated the VCCIO3C description for the following tables:
    • Table: Power Supply Sharing Guidelines for Intel® Stratix® 10 GX (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps.
    • Table: Power Supply Sharing Guidelines for Intel® Stratix® 10 GX (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
    • Table: Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps.
    • Table: Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps.
    • Table: Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
    • Table: Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
2023.04.03 Updated the HPS_COLD_nRESET signal description in Table: SDM Optional Signal Pins.
2022.06.25 Added reference to the Intel® Stratix® 10 Power Management User Guide in the Power Supply Pins section.
2022.04.01
  • Updated the connection guidelines of the GXP[L, R][10, 11, 12][A, B, C]_RX_CH[0:19][p,n] pins.
  • Updated the connection guidelines of the REFCLK_GXP[L, R][10, 11, 12][A, B, C]_CH[0, 2][p,n] pins.
2022.01.14 Updated the pin description and connection guidelines of the NAND_RB pin.
2021.12.13
  • Updated the pin description of the nSTATUS pin.
  • Updated the connection guidelines of the following pins to provide more clarity:
    • REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]p
    • REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]n
    • REFCLK_GXP[L, R][10, 11, 12][A, B, C]_CH[0, 2][p,n]
  • Updated the connection guidelines of the VCCH_GXP[L, R][1, 2, 3] pins.
2020.12.23
Removed the sentence "For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30 dB of isolation for a 1 MHz to 100 MHz bandwidth." from the following tables:
  • Power Supply Sharing Guidelines for Intel Stratix 10 GX with Transceiver Data Rate <= 15 Gbps
  • Power Supply Sharing Guidelines for Intel Stratix 10 GX (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps
  • Power Supply Sharing Guidelines for Intel Stratix 10 SX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
  • Power Supply Sharing Guidelines for Intel Stratix 10 SX (–2L and –3X parts) with Transceiver Data Rate <= 15 Gbps
  • Power Supply Sharing Guidelines for Intel Stratix 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps
  • Power Supply Sharing Guidelines for Intel Stratix 10 SX (–2L and –3X parts) (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps
  • Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
  • Power Supply Sharing Guidelines for Intel Stratix 10 MX (E-Tile) with L/H-Tile Transceiver Data Rate <= 15 Gbps and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps
  • Power Supply Sharing Guidelines for Intel Stratix 10 GX 10M with Transceiver Data Rate <= 15 Gbps
Note: If you have implemented this recommendation on your board and your design functions properly, you do not need to rework the board.
2020.12.14 Corrected the pin name RREF_SPIAUX0 to RREF_SIPAUX0 in Table: H-Tile and L-Tile Pins.
2020.11.23 Updated the regulator sharing for VCCM_WORD_(BL,TL) from share to isolate in the following tables:
  • Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with L/H-Tile Transceiver Data Rate <= 15 Gbps and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps
  • Power Supply Sharing Guidelines for Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) with 10 Gbps < P-Tile Transceiver Data Rate <= 16 Gbps, and 10 Gpbs < E-Tile Transceiver Data Rate <= 57.8 Gbps
2020.10.23
  • Added the RREF_SPIAUX0 pin in Table: H-Tile and L-Tile Pins.
  • Updated Table: HPS Supply Pins.
  • Updated the following tables:
    • Updated table title Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with Transceiver Data Rate <= 57.8 Gbps to Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with L/H-Tile Transceiver Data Rate <= 15 Gbps and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps.
    • Updated table title Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps to Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) with 15 Gbps < H-Tile Transceiver Data Rate <= 28.3 Gbps, and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps.
    • Updated table title Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps to Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 15 Gbps < H-Tile Transceiver Data Rate <= 28.3 Gbps, and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps.
    • Updated table title Power Supply Sharing Guidelines for Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) with 10 Gbps < P-Tile Transceiver Data Rate <= 16 Gbps, and 10 Gpbs < E-Tile Transceiver Data Rate <= 57.8 Gbps to Power Supply Sharing Guidelines for Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 16 Gbps.
  • Updated the following figures:
    • Updated figure title Example Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with Transceiver Data Rate <= 57.8 Gbps to Example Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with L/H-Tile Transceiver Data Rate <= 15 Gbps and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps.
    • Updated figure title Example Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps to Example Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) with 15 Gbps < H-Tile Transceiver Data Rate <= 28.3 Gbps, and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps.
    • Updated figure title Example Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps to Example Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 15 Gbps < H-Tile Transceiver Data Rate <= 28.3 Gbps, and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps.
    • Updated figure title Example Power Supply Sharing Guidelines for Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 16 Gbps to Example Power Supply Sharing Guidelines for Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) with 10 Gbps < P-Tile Transceiver Data Rate <= 16 Gbps, and 10 Gpbs < E-Tile Transceiver Data Rate <= 57.8 Gbps.
  • Updated the regulator sharing for VCCM_WORD_(BL,TL) from share to isolate in the following tables:
    • Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
  • Updated the notes for VCCM_WORD_(BL,TL) in the following tables:
    • Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 MX (E-Tile) with Transceiver Data Rate <= 57.8 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 DX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 16 Gbps
  • Updated the notes for VCCIO_SDM, VCCIO, and VCCIO3V in the following tables:
    • Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 MX (E-Tile) with Transceiver Data Rate <= 57.8 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 TX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
    • Power Supply Sharing Guidelines for Intel Stratix 10 DX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 16 Gbps
  • Removed the notes for VCCIO, and VCCIO3V in the following figures:
    • Example Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
    • Example Power Supply Sharing Guidelines for Intel Stratix 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Example Power Supply Sharing Guidelines for Intel Stratix 10 MX (E-Tile) with Transceiver Data Rate <= 57.8 Gbps
    • Example Power Supply Sharing Guidelines for Intel Stratix 10 TX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
    • Example Power Supply Sharing Guidelines for Intel Stratix 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
2020.08.07
  • Removed the preliminary tagging from the document.
  • Added Intel® Stratix® 10 GX 10M pins.
  • Added the following power supply sharing guidelines for Intel® Stratix® 10 GX 10M devices:
    • Example 19—Power Supply Sharing Guidelines for Intel® Stratix® 10 GX 10M with Transceiver Data Rate <= 15 Gbps.
    • Example 20—Power Supply Sharing Guidelines for Intel® Stratix® 10 GX 10M with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
  • Added the Physical Mapping of the Transceiver Channel Corresponding to the 3V I/O Bank table.
  • Added a note in the Intel® Stratix® 10 P-Tile Pins section to include details on the lane reversal and polarity inversion on the PCB.
  • Updated the pin description of the IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] pins.
  • Updated the connection guidelines of the GXE(L8, R9)(A, B, C)_RX_CH[0:23][p,n] pins.
  • Updated the pin description and connection guidelines of the REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8][p,n] pins.
  • Updated the connection guidelines of the NC pin.
  • Updated the connection guidelines of the U[10, 11, 12, 20, 21, 22]_P_IO_RESREF_0 pins.
  • Updated the Group 3 valid assignments for the SPIS1_MISO and SPIS1_SS0_N pins.
  • Updated note (1) in the following figures:
    • Figure 3—Example Power Supply Sharing Guidelines for Intel® Stratix® 10 GX (only for the HF35 Package) with Transceiver Data Rate ≤ 15 Gbps.
    • Figure 4—Example Power Supply Sharing Guidelines for Intel® Stratix® 10 GX (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
  • Updated note (2) in the following figures:
    • Figure 9—Example Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps.
    • Figure 10—Example Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps.
    • Figure 11—Example Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
    • Figure 12—Example Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
2020.06.30
  • Updated the connection guidelines of the TCK pin.
  • Updated the pin description of the nSTATUS pin.
  • Updated the connection guidelines of the nCONFIG pin.
  • Updated the AVST x8, x16, and x32 configuration schemes for the Direct to Factory Image signal in the SDM Optional Signal Pins table.
  • Updated Example 13—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps.
  • Updated Example 14—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
  • Updated Example 15—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with Transceiver Data Rate <= 57.8 Gbps.
  • Updated Example 16—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps.
  • Updated Example 17—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps.
  • Removed the SDMMC_CFG configuration pin functions and connection guidelines from the Secure Device Manager (SDM) Pins table.
2020.04.20
  • Added the pin description and connection guidelines of the DIFF_3[A,D]_[1:24][p,n] pins.
  • Added the pin description and connection guidelines of the IO33_[5:0]_[7:0] pins.
  • Added a note for the I/O pins in the 3V Compatible I/O Pins and Differential I/O Pins section.
  • Added the input reference clock guideline to the following pins:
    • CLK_ESRAM_[0,1]p
    • CLK_ESRAM_[0,1]n
    • UIB_PLL_REF_CLK_[00,01]p
    • UIB_PLL_REF_CLK_[00,01]n
    • REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]p
    • REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]n
    • REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8][p,n]
  • Updated the connection guidelines of the VSIGP_[0,1] and VSIGN_[0,1] pins.
  • Updated the connection guidelines of the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signal pins.
  • Updated the connection guidelines of the REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8][p,n] pins.
  • Updated the connection guidelines of the U[10, 11, 12, 20, 21, 22]_P_IO_RESREF_0 pins.
  • Added Example 3—Power Supply Sharing Guidelines for Intel® Stratix® 10 GX (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps.
  • Added Example 4—Power Supply Sharing Guidelines for Intel® Stratix® 10 GX (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
  • Added Example 9—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps.
  • Added Example 10—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) with Transceiver Data Rate <= 15 Gbps.
  • Added Example 11—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
  • Added Example 12—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
  • Added Example 15—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with Transceiver Data Rate <= 57.8 Gbps.
  • Updated Example 14—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps.
  • Updated Example 16—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps.
  • Updated Example 17—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps.
2019.12.13 Updated the jitter specification of the UIB_PLL_REF_CLK_[00,01]p and UIB_PLL_REF_CLK_[00,01]n pins.
2019.12.11
  • Updated the connection guidelines of the IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] pins.
  • Updated the connection guidelines of the VCCIO3V pin.
2019.09.20 Added support for Intel® Stratix® 10 DX devices.
  • Added Intel® Stratix® 10 P-Tile Power Supply Pins section.
  • Added Intel® Stratix® 10 P-Tile Transceiver Pins section.
  • Added Example 11—Power Supply Sharing Guidelines for Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 16 Gbps.
2019.07.01
  • Added the following note to Figures 2, 5, 6, 8, 9, and 10:
    • For data rates less than equal to 17.4 Gbps, you may source VCCR_GXB from the same VCCT_GXB regulator using a ferrite bead filter to isolate VCCR_GXB from VCCT_GXB.
  • Updated the connection guidelines for the IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] pins.
  • Updated the connection guidelines for the REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8]p and REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8]n pins.
  • Updated the connection guidelines for the PWRMGT_SCL, PWRMGT_ALERT, and PWRMGT_SDA pin functions in the SDM_IO pins.
  • Updated the connection guidelines for the UIB_PLL_REF_CLK_[00,01]p and UIB_PLL_REF_CLK_[00,01]n pins.
  • Updated the connection guidelines for the SDMMC_DATA3 pin.
  • Updated the connection guidelines of the GXE(L8, R9)(A, B, C)_RX_CH[0:23][p,n] pins.
  • Updated the pin functions and connection guidelines for the Secure Device Manager (SDM) Pins section and added the Secure Device Manager (SDM) Optional Signal Pins section.
  • Updated the pin description and connection guidelines of the JTAG_TCK pin.
  • Updated VCCIO_UIB to Power Group 3 in the following figures:
    • Figure 7—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
    • Figure 8—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
  • Removed support for the VREFP_ADC and VREFN_ADC pins.
2019.06.14 Updated the following power supply sharing guidelines to remove VCCL_HPS, VCCPLLDIG_HPS, VCCIO_HPS, and VCCPLL_HPS power rails:
  • Example 7—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
  • Example 8—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
2019.01.31
  • Added a note to include the H-tile and E-tile transceivers' reference in the Intel® Stratix® 10 MX Pin Connection Guidelines section.
  • Removed 0.8V support for VCC and VCCP supplies for the fixed voltage –2L and –3X devices in the following power supply sharing guidelines:
    • Example 1—Power Supply Sharing Guidelines for Intel® Stratix® 10 GX with Transceiver Data Rate <= 15 Gbps
    • Example 2—Power Supply Sharing Guidelines for Intel® Stratix® 10 GX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Example 4—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) with Transceiver Data Rate <= 15 Gbps
    • Example 6—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Example 10—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
  • Removed VCCM_WORD and VCCIO_UIB supplies from the following power supply sharing guidelines:
    • Example 9—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
    • Example 10—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
2019.01.03
  • Updated the connection guidelines for the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] pins.
  • Updated the notes of the VCCR_GXB[L,R] and VCCT_GXB[L,R] in the following power supply sharing guidelines:
    • Example 1—Power Supply Sharing Guidelines for Intel® Stratix® 10 GX with Transceiver Data Rate <= 15 Gbps
    • Example 2—Power Supply Sharing Guidelines for Intel® Stratix® 10 GX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Example 3—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
    • Example 4—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) with Transceiver Data Rate <= 15 Gbps
    • Example 5—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Example 6—Power Supply Sharing Guidelines for Intel® Stratix® 10 SX (–2L and –3X parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Example 7—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with Transceiver Data Rate <= 15 Gbps
    • Example 8—Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Example 9—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
    • Example 10—Power Supply Sharing Guidelines for Intel® Stratix® 10 TX (–2L and –3X parts) with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps
2018.12.14
  • Added Direct to Factory Image pin function to SDM_IO0, SDM_IO10, SDM_IO11, SDM_IO12, SDM_IO13, SDM_IO14, SDM_IO15, and SDM_IO16 pins.
  • Added SEU_ERROR and CvP_CONFDONE pin functions to SDM_IO0, SDM_IO10, SDM_IO11, SDM_IO12, SDM_IO13, SDM_IO14, SDM_IO15, and SDM_IO16 pins.
  • Added a description to Transceiver Pins section for reference to the OSC_CLK_1 pin.
  • Updated the pin description and connection guidelines of the OSC_CLK_1 pin.
  • Updated the connection guidelines of the nCONFIG pin.
  • Updated the pin function and connection guidelines of the nSTATUS pin.
  • Updated the pin description and connection guidelines of the IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] pins.
  • Updated the pin description and connection guidelines of the VCCFUSEWR_SDM pin.
  • Updated the connection guidelines of the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N], and VCCH_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N] pins.
  • Updated the connection guidelines of the REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]p and REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]n pins.
  • Updated the pin description for the INIT_DONE function in SDM_IO0, SDM_IO5, and SDM_IO16 pins.
  • Updated the connection guidelines of the VCCRT_GXE(L2, L3, R1, R2, R3) and VCCRTPLL_GXE(L2, L3, R1, R2, R3) pins.
  • Updated the connection guidelines of the HPS_COLD_nRESET function in SDM_IO0, SDM_IO10, SDM_IO11, SDM_IO12, SDM_IO13, SDM_IO14, SDM_IO15, and SDM_IO16 pins.
  • Updated the connection guidelines of the CLK_ESRAM_[0,1]p and CLK_ESRAM_[0,1]n pins.
  • Updated the following power supply sharing guidelines:
    • Example 7— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts)
    • Example 8— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts)
    • Example 9— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts)
    • Example 10— Intel® Stratix® 10 TX (–2L and –3X parts)
  • Removed the following power supply sharing guidelines:
    • Intel® Stratix® 10 MX (–2L and –3X parts)
  • Removed support for the Pulse-Width Modulation (PWM) mode.
  • Removed a note regarding the SEU_ERROR and CvP_CONFDONE pins from the Notes to Intel® Stratix® 10 GX Pin Connection Guidelines section and added the connection guidelines of the SEU_ERROR and CvP_CONFDONE pins in their respective SDM pin functions.
2018.08.16
  • Added description that these pins can be used for the HPS in the TCK, TMS, TDO, TDI, JTAG_TCK, JTAG_TMS, JTAG_TDO, and JTAG_TDI pins.
  • Added note 13 to the Notes to Intel® Stratix® 10 GX Pin Connection Guidelines section.
  • Added the HPS_COLD_nRESET function to SDM_IO0, SDM_IO10, SDM_IO11, SDM_IO12, SDM_IO13, SDM_IO14, SDM_IO15, and SDM_IO16 pins.
  • Added a description to Transceiver Pins section for reference to the nPERST[L,R][0:2] pins.
  • Added the PWRMGT_ALERT pin function in the SDM_IO0 and SDM_IO12 pins.
  • Updated the connection guidelines of the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] pins.
  • Updated the VCCH_GXB[L,R] pin name to VCCH_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N].
  • Updated the connection guidelines for the GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_RX_CH[0:5]p, GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_REFCLK[0:5]p, GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_RX_CH[0:5]n, and GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_REFCLK[0:5]n pins.
  • Updated the pin description for the REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]p and REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]n pins.
  • Updated the connection guidelines of the VCCIO3V pin.
  • Updated the connection guidelines for the –V device for the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_PWM0 pin functions of the SDM_IO pins.
  • Updated the connection guidelines of the VCCRTPLL_GXE(L2, L3, R1, R2, R3) pins.
  • Updated the connection guidelines to leave the unused pins floating of the GXE(L8, R9)(A, B, C)_RX_CH[0:23]p and GXE(L8, R9)(A, B, C)_RX_CH[0:23]n pins.
  • Updated the connection guidelines of the REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8]p and REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8]n pins.
  • Updated the connection guidelines of the VCCL_HPS pin.
  • Updated note 12 in the Notes to Intel® Stratix® 10 GX Pin Connection Guidelines.
  • Updated the Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices section to include references for the power-up and power-down sequence requirements.
  • Removed support of the NAND configuration scheme.
  • Added the following power supply sharing guidelines:
    • Example 4— Intel® Stratix® 10 SX (–2L and –3X parts)
    • Example 6— Intel® Stratix® 10 SX (–2L and –3X parts)
    • Example 8— Intel® Stratix® 10 MX (–2L and –3X parts)
    • Example 10— Intel® Stratix® 10 MX (–2L and –3X parts)
    • Example 12— Intel® Stratix® 10 TX (–2L and –3X parts)
  • Updated the following power supply sharing guidelines:
    • Example 3— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts)
    • Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts)
    • Example 7— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts)
    • Example 9— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts)
    • Example 11— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts)
Date Version Description of Changes
December 2017 2017.12.21
  • Added the following Intel® Stratix® 10 TX pins:
    • VCCH_GXE(L2, L3, R1, R2, R3)
    • VCCRT_GXE(L2, L3, R1, R2, R3)
    • VCCRTPLL_GXE(L2, L3, R1, R2, R3)
    • VCCCLK_GXE(L2, L3, R1, R2, R3)
    • GXE(L8, R9)(A, B, C)_RX_CH[0:23]p
    • GXE(L8, R9)(A, B, C)_RX_CH[0:23]n
    • GXE(L8, R9)(A, B, C)_TX_CH[0:23]p
    • GXE(L8, R9)(A, B, C)_TX_CH[0:23]n
    • REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8]p
    • REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8]n
    • IO_AUX_RREF(11, 12, 20, 21, 22)
  • Added the following HPS sections:
    • HPS Oscillator Clock Input Pin
    • HPS JTAG Pins
    • HPS GPIO Pins
    • HPS SDMMC Pins
    • HPS NAND Pins
    • HPS USB Pins
    • HPS EMAC Pins
    • HPS I2C_EMAC and MDIO Pins
    • HPS I2C Pins
    • HPS SPI Pins
    • HPS UART Pins
    • HPS Trace Pins
  • Added the Power Supply Sharing Guidelines for Intel® Stratix® 10 TX with 10 Gbps < Transceiver Data Rate <= 57.8 Gbps.
  • Updated the following pin names:
    • CLK_ESRAM_[0,1]p
    • CLK_ESRAM_[0,1]n
    • RREF_ESRAM_[0,1]
  • Updated the connection guidelines for the following pins:
    • CLK_ESRAM_[0,1]p
    • CLK_ESRAM_[0,1]n
    • UIB_PLL_REF_CLK_[00,01]p
    • UIB_PLL_REF_CLK_[00,01]n
  • Updated the connection guidelines for the VREFP_ADC and VREFN_ADC pins.
  • Updated the connection guidelines for the TEMPDIODEp[0..6] and TEMPDIODEn[0..6] pins.
  • Updated the connection guidelines for the VCCLSENSE and GNDSENSE pins.
  • Updated the connection guidelines for the OSC_CLK_1 pin.
  • Updated the connection guidelines for the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] pins.
  • Updated the pin names for the VCCM_WORD_(BL,TL) and VCCIO_UIB_(BL,TL) pins.
  • Updated the pin description for all SDM_IO pins to include the resistor information upon device power up.
  • Updated the pin description for the INIT_DONE function in SDM_IO0, SDM_IO5, and SDM_IO16.
  • Updated the pin description of the PWRMGT_SCL function in the SDM_IO0 and SDM_IO14 pins.
  • Updated the pin description of the PWRMGT_SDA function in the SDM_IO11, SDM_IO12, and SDM_IO16 pins.
  • Updated note 12 in the Notes to Intel® Stratix® 10 GX Pin Connection Guidelines.
  • Added a note for the VCCL_HPS, VCCPLL_HPS, VCCIO_HPS, and VCCPLLDIG_HPS power rails in the following power supply sharing guidelines:
    • Power Supply Sharing Guidelines for Intel® Stratix® 10 SX with Transceiver Data Rate <= 15 Gbps
    • Power Supply Sharing Guidelines for Intel® Stratix® 10 SX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
July 2017 2017.07.14 Added the TEMPDIODEp[0..6] and TEMPDIODEn[0..6] pins.
June 2017 2017.06.16
  • Added the INIT_DONE function to SDM_IO5 and SDM_IO16 pins.
  • Added link to the External Memory Interface Pin Information for Intel® Stratix® 10 Devices.
  • Updated the connection guidelines of the PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FB[0], PLL_[3][A,B,C,F,G,H,I,J,K,L]_FB[0], PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBp, PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBp, PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBn, PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1], PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1], PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]p, PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]p, PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]n, and PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]n pins.
  • Updated the pin description and connection guidelines of the OSC_CLK_1 pin.
  • Updated the I/O standards supported in the pin description of the IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] pins.
  • Updated the pin functions and connection guidelines of the RZQ_[2] [A,B,C,F,G,H,I,J,K,L,M ,N] and RZQ_[3] [A,B,C,D,E,F,G,H,I,J,K ,L] pins.
  • Updated the connection guidelines of the VCCIO([2][A,B,C,F,L,M,N],[3][A,B,C,I,J,K,L]) pins.
  • Updated the pin description of the VCCERAM.
  • Updated the connection guidelines of the VCCFUSEWR_SDM pin.
  • Updated the connection guidelines of the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N] pins.
  • Updated the pin description for the CONF_DONE function in the SDM_IO5 pin.
  • Added the INIT_DONE function to SDM_IO5 and SDM_IO16 pins.
  • Updated note 12 in the Notes to Stratix 10 GX and MX Pin Connecti0n Guidelines.
  • Updated the VCCL_HPS and VCCPLLDIG_HPS supply to 0.94V.
  • Updated the connection guidelines for the VCCL_HPS pin.
  • Updated the notes for VCC and VCCP power rails in the following tables:
    • Power Supply Sharing Guidelines for Stratix 10 GX with Transceiver Data Rate <= 15 Gbps
    • Power Supply Sharing Guidelines for Stratix 10 GX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
  • Updated the notes for VCC, VCCP, VCCL_HPS, and VCCPLLDIG_HPS power rails in the following examples:
    • Power Supply Sharing Guidelines for Stratix 10 SX with Transceiver Data Rate <= 15 Gbps
    • Power Supply Sharing Guidelines for Stratix 10 SX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Power Supply Sharing Guidelines for Stratix 10 MX with Transceiver Data Rate <= 15 Gbps
    • Power Supply Sharing Guidelines for Stratix 10 MX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
  • Updated voltage of the VCCL_HPS and VCCPLLDIG_HPS supply in note 1 of the following figures:
    • Example Power Supply Sharing Guidelines for Stratix 10 SX with Transceiver Data Rate <= 15 Gbps
    • Example Power Supply Sharing Guidelines for Stratix 10 SX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
    • Example Power Supply Sharing Guidelines for Stratix 10 MX with Transceiver Data Rate <= 15 Gbps
    • Example Power Supply Sharing Guidelines for Stratix 10 MX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
  • Updated the VCCM's tolerance to ± 100mV.
  • Removed PowerPlay text from tool name.
February 2017 2017.02.24
  • Added the following pins for the MX device variant:
    • VCCM[B,T]
    • VCCIO_UIB_[B,T]
    • ESRAM_PLL_REF_CLK_[0,1]p
    • ESRAM_PLL_REF_CLK_[0,1]n
    • UIB_PLL_REF_CLK_[00,01,10,11]p
    • UIB_PLL_REF_CLK_[00,01,10,11]n
    • ESRAM_RREF_[B,T]
    • UIB_RREF_[00,01,10,11]
  • Added the following power supply sharing guidelines for the MX device variant:
    • Example 5. Power Supply Sharing Guidelines for Stratix 10 MX with Transceiver Data Rate <= 15 Gbps
    • Example 6. Power Supply Sharing Guidelines for Stratix 10 MX with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
  • Updated IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] pin name.
  • Updated the connection guidelines for the SDM_IO13 pin.
  • Updated the pin description of the CONF_DONE function in SDM_IO5 and SDM_IO16 pins.
  • Updated note 7 in the Notes to Stratix 10 GX and MX Pin Connecti0n Guidelines.
  • Updated note 6 in the Notes to Stratix 10 SX Pin Connection Guidelines.
  • Updated the transceiver data rate from 30 Gbps to 28.3 Gbps.
October 2016 2016.10.31 Initial release.
Level Two Title