Intel® Stratix® 10 Device Family Pin Connection Guidelines

Download PDF
ID 683028
Date 12/29/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Device Family Pin Connection Guidelines x
Intel® Stratix® 10 Core Pins Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Intel® Stratix® 10 E-Tile Pins Intel® Stratix® 10 P-Tile Pins Intel® Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins 3.3V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Intel® Stratix® 10 HBM Power Supply Pins Notes to Intel® Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins x
Intel® Stratix® 10 E-Tile Pins Notes to Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins x
Intel® Stratix® 10 P-Tile Power Supply Pins Intel® Stratix® 10 P-Tile Transceiver Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Intel® Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices x
Example 1— Intel® Stratix® 10 GX Example 2— Intel® Stratix® 10 GX Example 3— Intel® Stratix® 10 GX (only for the HF35 Package) Example 4— Intel® Stratix® 10 GX (only for the HF35 Package) Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Intel® Stratix® 10 SX (–2L and –3X parts) Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Intel® Stratix® 10 SX (–2L and –3X parts) Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Intel® Stratix® 10 MX (E-Tile) Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Intel® Stratix® 10 TX (–2L and –3X parts) Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Intel® Stratix® 10 GX 10M Example 20— Intel® Stratix® 10 GX 10M
Intel® Stratix® 10 Device Family Pin Connection Guidelines

Intel® Stratix® 10 E-Tile Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 19.   Intel® Stratix® 10 E-Tile Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCH_GXE(L2, L3, R1, R2, R3) Power Analog power, block level transmitter buffers for E-tile, specific to the left (L) side or right (R) side of the device.

Connect VCCH_GXE to a 1.1V low noise switching regulator.

VCCH_GXE must be powered up even when the E-tile transceivers are not used.
VCCRT_GXE(L2, L3, R1, R2, R3) Power Analog power, used for the high-speed circuitry for the E-tile blocks, specific to the left (L) side or right (R) side of the device.

Connect VCCRT_GXE to VCCERAM through an LC filter. For more information about the LC filter design, refer to the Intel® Stratix® 10 Power Management User Guide.

VCCRT_GXE must be powered up even when the E-tile transceivers are not used.
VCCRTPLL_GXE(L2, L3, R1, R2, R3) Power Analog power, used for the high-speed circuitry for the E-tile blocks, specific to the left (L) side or right (R) side of the device.

You must source the VCCRTPLL_GXE from the VCCRT_GXE with proper isolation filtering.

Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel® Stratix® 10 Power Management User Guide.

VCCRTPLL_GXE must be powered up even when the E-tile transceivers are not used.
VCCCLK_GXE(L2, L3, R1, R2, R3) Power I/O power, specific to the E-tile reference clock buffers.

Connect VCCCLK_GXE to a 2.5V low noise switching regulator.

VCCCLK_GXE must be powered up even when the E-tile transceivers are not used.

GXE(L8, R9)(A, B, C)_RX_CH[0:23][p,n]

Input High speed differential serial inputs to the receiver circuitry. Specific to the E-tile transceiver blocks on the left (L) side or right (R) side of the device.

For PAM4, no off-chip AC-coupling capacitor is required provided that the RX input common mode voltage is between (GND + 300mV) and (VCCH_GXE-300mV), and the RX input amplitude differential voltage is less than 1200mVp-p. For PAM4, the absolute maximum positive voltage at the RX input of the SerDes is VCCH_GXE to maintain linearity.

For NRZ, no off-chip AC-coupling capacitor is required provided that the RX input common mode voltage is between GND and VCCH_GXE, and the RX input amplitude differential voltage is less than 1200mVp-p. For NRZ, the absolute maximum positive voltage at the RX input to the SerDes is (VCCH_GXE + 300mV) to prevent forward-biasing of the ESD diodes.

For more information, refer to the Electrical Characteristics section in the Intel® Stratix® 10 Device Datasheet.

When the RX input common mode voltage is outside its required range (PAM4 or NRZ), external AC-coupling capacitors must be used. When using external AC-coupling capacitors, the RX termination is to the VCCH_GXE supply. A typical value of 100nF can be used as the external AC-coupling capacitor. Select a capacitor package (SMD) similar to that of the trace width to reduce in-line parasitics, and a material of X7R quality or higher. For high speed SerDes, mounting launch pad must be carefully designed.

For more information about the external AC-coupling, refer to the Intel® Stratix® 10 E-Tile Transceiver PHY User Guide.

Leave unused pins floating.
GXE(L8, R9)(A, B, C)_TX_CH[0:23][p,n] Output High speed differential serial outputs from the transmitter circuitry. Specific to the E-tile transceiver blocks on the left (L) side or right (R) side of the device. Leave all unused GXE_TX[p,n] pins floating.
REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8][p,n] Input

High speed differential reference clock connects to the E-tile transceiver of the left (L) side or right (R) side of the device.

REFCLK_GXE is supplied to both RX and TX independently.

REFCLK_GXE can be used as dedicated clock input pins for core clock generation by configuring transceiver channel (Native PHY IP core) in the PLL mode.

Supported I/O standard:

  • LVPECL

No off-chip AC-coupling capacitor is required. The default internal REFCLK inputs are 2.5-V LVPECL with a 50-Ω termination.

Optional external termination is 2.5-V LVPECL or 3.3-V LVPECL. For more information about the external termination, refer to section 4.1 in the E-Tile Transceiver PHY User Guide.

Tie each unused REFCLK pin to GND through a 1-kΩ resistor.

REFCLK[1] must always be bonded out on board and connected to a clock source in case dynamic reconfiguration of REFCLK is planned. For more details on how to use it, refer to section 7.12 in the E-tile Transceiver PHY User Guide.

Preservation of unused transceiver channels may need extra REFCLK_GXE to be bonded out on board based on use cases. For more details, refer to section 3.1.10 Unused Transceiver Channel in the E-tile Transceiver PHY User Guide.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

IO_AUX_RREF(11, 12, 20, 21, 22) Input Reference resistor for the AIB auxiliary channel. Connect to a 2-kΩ resistor (±1%) to GND.
Related Information
Level Two Title