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Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices
Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Clock and PLL Pins
Dedicated Configuration/JTAG Pins
Optional/Dual-Purpose Configuration Pins
3V Compatible I/O Pins
3.3V I/O Pins
Differential I/O Pins
External Memory Interface Pins
Voltage Sensor Pins
Temperature Sensor Pins
Reference Pins
No Connect and DNU Pins
Power Supply Pins
Secure Device Manager (SDM) Pins
Secure Device Manager (SDM) Optional Signal Pins
Notes to Intel® Stratix® 10 Core Pins
Example 1— Intel® Stratix® 10 GX
Example 2— Intel® Stratix® 10 GX
Example 3— Intel® Stratix® 10 GX (only for the HF35 Package)
Example 4— Intel® Stratix® 10 GX (only for the HF35 Package)
Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts)
Example 6— Intel® Stratix® 10 SX (–2L and –3X parts)
Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts)
Example 8— Intel® Stratix® 10 SX (–2L and –3X parts)
Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package)
Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package)
Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package)
Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package)
Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts)
Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts)
Example 15— Intel® Stratix® 10 MX (E-Tile)
Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts)
Example 17— Intel® Stratix® 10 TX (–2L and –3X parts)
Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts)
Example 19— Intel® Stratix® 10 GX 10M
Example 20— Intel® Stratix® 10 GX 10M
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HPS SPI Pins
Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the group) | ||
---|---|---|---|---|---|
Group 1 | Group 2 | Group 3 | |||
SPIM0_CLK | SPIM0 Clock | Output | HPS_IOA_5 | HPS_IOB_21 | HPS_IOB_21 |
SPIM0_MOSI | SPIM0 Master Out Slave In | Output | HPS_IOA_6 | HPS_IOB_22 | HPS_IOB_22 |
SPIM0_MISO | SPIM0 Master In Slave Out | Input | HPS_IOA_7 | HPS_IOB_19 | HPS_IOB_23 |
SPIM0_SS0_N | SPIM0 Slave Select 0 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_8 | HPS_IOB_20 | HPS_IOB_24 |
SPIM0_SS1_N | SPIM0 Slave Select 1 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_1 | HPS_IOB_18 | HPS_IOB_18 |
SPIM1_CLK | SPIM1 Clock | Output | HPS_IOA_9 | HPS_IOA_21 | HPS_IOB_1 |
SPIM1_MOSI | SPIM1 Master Out Slave In | Output | HPS_IOA_10 | HPS_IOA_22 | HPS_IOB_2 |
SPIM1_MISO | SPIM1 Master In Slave Out | Input | HPS_IOA_11 | HPS_IOA_23 | HPS_IOB_3 |
SPIM1_SS0_N | SPIM1 Slave Select 0 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_12 | HPS_IOA_24 | HPS_IOB_4 |
SPIM1_SS1_N | SPIM1 Slave Select 1 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Output | HPS_IOA_2 | HPS_IOA_20 | HPS_IOB_5 |
SPIS0_CLK | SPIS0 Clock | Input | HPS_IOA_1 | HPS_IOA_21 | HPS_IOB_9 |
SPIS0_MOSI | SPIS0 Master Out Slave In | Input | HPS_IOA_2 | HPS_IOA_22 | HPS_IOB_10 |
SPIS0_MISO | SPIS0 Master In Slave Out | Output | HPS_IOA_4 | HPS_IOA_24 | HPS_IOB_12 |
SPIS0_SS0_N | SPIS0 Slave Select 0 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Input | HPS_IOA_3 | HPS_IOA_23 | HPS_IOB_11 |
SPIS1_CLK | SPIS1 Clock | Input | HPS_IOA_9 | HPS_IOB_5 | HPS_IOB_21 |
SPIS1_MOSI | SPIS1 Master Out Slave In | Input | HPS_IOA_10 | HPS_IOB_6 | HPS_IOB_22 |
SPIS1_MISO | SPIS1 Master In Slave Out | Output | HPS_IOA_12 | HPS_IOB_8 | HPS_IOB_24 |
SPIS1_SS0_N | SPIS1 Slave Select 0 See Note 11 in Notes to Intel® Stratix® 10 HPS Pins. |
Input | HPS_IOA_11 | HPS_IOB_7 | HPS_IOB_23 |