Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

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ID 683093
Date 5/03/2019
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Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Stratix V Hard IP for PCI Express 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design 4. Parameter Settings 5. Interfaces and Signal Descriptions 6. Registers 7. Interrupts 8. Error Handling 9. PCI Express Protocol Stack 10. Transaction Layer Protocol (TLP) Details 11. Throughput Optimization 12. Design Implementation 13. Additional Features 14. Hard IP Reconfiguration 15. Transceiver PHY IP Reconfiguration 16. Testbench and Design Example 17. Debugging A. Frequently Asked Questions for PCI Express B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Stratix V Avalon-ST Interface for PCIe Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Configurations 1.5. Avalon-ST Example Designs 1.6. Debug Features 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.1. Stratix V Avalon-ST Interface for PCIe Datasheet x
1.1.1. Features
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Stratix V Hard IP for PCI Express x
2.1. Qsys Design Flow
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Simulation Log File Generation 2.1.6. Understanding Physical Placement of the PCIe IP Core 2.1.7. Compiling the Design in the Qsys Design Flow 2.1.8. Modifying the Example Design 2.1.9. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design x
3.1. Copying the Configuration Space Bypass Mode Example Design 3.2. Generating the Qsys System 3.3. Simulating the Example Design
3.2. Generating the Qsys System x
3.2.1. Generating Synthesis Files 3.2.2. Understanding the Generated Files 3.2.3. Understanding Simulation Log File Generation
3.3. Simulating the Example Design x
3.3.1. Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface 3.3.2. Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface 3.3.3. Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface 3.3.4. Partial Transcript for Configuration Space Bypass Simulation
4. Parameter Settings x
4.1. System Settings 4.2. Base Address Register (BAR) and Expansion ROM Settings 4.3. Base and Limit Registers for Root Ports 4.4. Device Identification Registers 4.5. PCI Express and PCI Capabilities Parameters 4.6. Vendor Specific Extended Capability (VSEC) 4.7. PHY Characteristics
4.5. PCI Express and PCI Capabilities Parameters x
4.5.1. PCI Express and PCI Capabilities 4.5.2. Error Reporting 4.5.3. Link Capabilities 4.5.4. MSI and MSI-X Capabilities 4.5.5. Slot Capabilities 4.5.6. Power Management
5. Interfaces and Signal Descriptions x
5.1. Clock Signals 5.2. Reset, Status, and Link Training Signals 5.3. ECRC Forwarding 5.4. Error Signals 5.5. Interrupts for Endpoints 5.6. Interrupts for Root Ports 5.7. Completion Side Band Signals 5.8. Configuration Space Bypass Mode Interface Signals 5.9. Parity Signals 5.10. LMI Signals 5.11. Transaction Layer Configuration Space Signals 5.12. Hard IP Reconfiguration Interface 5.13. Power Management Signals 5.14. Physical Layer Interface Signals
5.11. Transaction Layer Configuration Space Signals x
5.11.1. Configuration Space Register Access Timing 5.11.2. Configuration Space Register Access
5.14. Physical Layer Interface Signals x
5.14.1. Transceiver Reconfiguration 5.14.2. Serial Data Signals 5.14.3. PIPE Interface Signals 5.14.4. Test Signals
5.14.2. Serial Data Signals x
5.14.2.1. Physical Layout of Hard IP in Stratix V GX/GT/GS Devices 5.14.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. CvP Registers 6.7. Uncorrectable Internal Error Mask Register 6.8. Uncorrectable Internal Error Status Register 6.9. Correctable Internal Error Mask Register 6.10. Correctable Internal Error Status Register
7. Interrupts x
7.1. Interrupts for Endpoints 7.2. Interrupts for Root Ports
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
9. PCI Express Protocol Stack x
9.1. Top-Level Interfaces 9.2. Transaction Layer 9.3. Data Link Layer 9.4. Physical Layer
9.1. Top-Level Interfaces x
9.1.1. Avalon-ST Interface 9.1.2. Clocks and Reset 9.1.3. Local Management Interface (LMI Interface) 9.1.4. Hard IP Reconfiguration 9.1.5. Transceiver Reconfiguration 9.1.6. Interrupts 9.1.7. PIPE
9.2. Transaction Layer x
9.2.1. Configuration Space 9.2.2. Configuration Space Bypass Mode
10. Transaction Layer Protocol (TLP) Details x
10.1. Supported Message Types 10.2. Transaction Layer Routing Rules 10.3. Receive Buffer Reordering
10.1. Supported Message Types x
10.1.1. INTX Messages 10.1.2. Power Management Messages 10.1.3. Error Signaling Messages 10.1.4. Locked Transaction Message 10.1.5. Slot Power Limit Message 10.1.6. Vendor-Defined Messages 10.1.7. Hot Plug Messages
10.3. Receive Buffer Reordering x
10.3.1. Using Relaxed Ordering
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Design Implementation x
12.1. Making Analog QSF Assignments Using the Assignment Editor 12.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 12.3. Recommended Reset Sequence to Avoid Link Training Issues 12.4. SDC Timing Constraints
13. Additional Features x
13.1. Configuration over Protocol (CvP) 13.2. Autonomous Mode 13.3. ECRC
13.2. Autonomous Mode x
13.2.1. Enabling Autonomous Mode 13.2.2. Enabling CvP Initialization
13.3. ECRC x
13.3.1. ECRC on the RX Path 13.3.2. ECRC on the TX Path
15. Transceiver PHY IP Reconfiguration x
15.1. Connecting the Transceiver Reconfiguration Controller IP Core 15.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
16. Testbench and Design Example x
16.1. Endpoint Testbench 16.2. Root Port Testbench 16.3. Test Driver Module 16.4. Root Port Design Example 16.5. Root Port BFM Overview 16.6. BFM Procedures and Functions 16.7. Setting Up Simulation
16.1. Endpoint Testbench x
16.1.1. Endpoint Testbench for SR-IOV
16.5. Root Port BFM Overview x
16.5.1. BFM Memory Map 16.5.2. Configuration Space Bus and Device Numbering 16.5.3. Configuration of Root Port and Endpoint 16.5.4. Issuing Read and Write Transactions to the Application Layer
16.6. BFM Procedures and Functions x
16.6.1. ebfm_barwr Procedure 16.6.2. ebfm_barwr_imm Procedure 16.6.3. ebfm_barrd_wait Procedure 16.6.4. ebfm_barrd_nowt Procedure 16.6.5. ebfm_cfgwr_imm_wait Procedure 16.6.6. ebfm_cfgwr_imm_nowt Procedure 16.6.7. ebfm_cfgrd_wait Procedure 16.6.8. ebfm_cfgrd_nowt Procedure 16.6.9. BFM Configuration Procedures 16.6.10. BFM Shared Memory Access Procedures 16.6.11. BFM Log and Message Procedures 16.6.12. Verilog HDL Formatting Functions
16.6.9. BFM Configuration Procedures x
16.6.9.1. ebfm_cfg_rp_ep Procedure 16.6.9.2. ebfm_cfg_decode_bar Procedure
16.6.10. BFM Shared Memory Access Procedures x
16.6.10.1. Shared Memory Constants 16.6.10.2. shmem_write Task 16.6.10.3. shmem_read Function 16.6.10.4. shmem_display Verilog HDL Function 16.6.10.5. shmem_fill Procedure 16.6.10.6. shmem_chk_ok Function
16.6.11. BFM Log and Message Procedures x
16.6.11.1. ebfm_display Verilog HDL Function 16.6.11.2. ebfm_log_stop_sim Verilog HDL Function 16.6.11.3. ebfm_log_set_suppressed_msg_mask Task 16.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 16.6.11.5. ebfm_log_open Verilog HDL Function 16.6.11.6. ebfm_log_close Verilog HDL Function
16.6.12. Verilog HDL Formatting Functions x
16.6.12.1. himage1 16.6.12.2. himage2 16.6.12.3. himage4 16.6.12.4. himage8 16.6.12.5. himage16 16.6.12.6. dimage1 16.6.12.7. dimage2 16.6.12.8. dimage3 16.6.12.9. dimage4 16.6.12.10. dimage5 16.6.12.11. dimage6 16.6.12.12. dimage7
16.7. Setting Up Simulation x
16.7.1. Changing Between Serial and PIPE Simulation 16.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 16.7.3. Viewing the Important PIPE Interface Signals 16.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 16.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 16.7.6. Changing between the Hard and Soft Reset Controller
17. Debugging x
17.1. Hardware Bring-Up Issues 17.2. Link Training 17.3. Use Third-Party PCIe Analyzer 17.4. BIOS Enumeration Issues
17.2. Link Training x
17.2.1. Debugging Link that Fails To Reach L0 17.2.2. Link Hangs in L0 State
C. Document Revision History x
C.1. Document Revision History Stratix V Avalon® -ST Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Stratix V Hard IP for PCI Express
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
4. Parameter Settings
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Transceiver PHY IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History

5.8. Configuration Space Bypass Mode Interface Signals

In Configuration Space Bypass mode, the soft Configuration Space exchanges control and status information with the Stratix V Hard IP for PCI Express’s Transaction, Data Link and PHY Layers.

Table 31.  Configuration Space Bypass Mode Input Signals Input signals are driven from the Application Layer’s soft Configuration Space to the Transaction Layer’s hard Configuration Space. All signals are synchronous to pld_clk.

Signal Name

Direction

Description

link2csr[12:0]

Input

Bits[12:0] of the link2csr register from the soft Configuration Space.

comclk_reg

Input

Common clock configuration bit of the Link Control register in the soft Configuration Space.

extsy_reg

Input

Extended synchronization bit of the Link Control register in the soft Configuration Space.

max_pload[2:0]

Input

MAX_PAYLOAD_SIZE field of the Device Control register in the soft Configuration Space.

tx_ecrcgen

Input

ECRC Generation Enable which is bit 6 of the Advanced Error Capabilities and Control register (0x18) in the soft Configuration Space.

rx_ecrchk

Input

ECRC Check Enable which is Bit 8 of the Advanced Error Capabilities and Control register (0x18) in the soft Configuration Space.

secbus[7]

Input

MSB of the Secondary Bus Number register in the soft Configuration Space.

secbus[6:0]

Input

Low-order 7 bits of Secondary Bus Number register in the soft Configuration Space.

linkcsr_bit0

Input

Active State Power Management(ASPM)Control which is Bit 0 of the Link Control register in the soft Configuration Space. ASPM is not supported.

tx_req_pm

Input

Assert this signal to request that the TX Data Link Layer send a Power Management Data Link Layer Packet of type tx_typ_pm_pld. Deasserts when tx_ack_pm_pld is asserted.

tx_typ_pm[2:0]

Input

Lowest 3 bits of the type field for the Power Management Data Link Layer Packet being requested by tx_req_pm_pld.

req_phypm[3:0]

Input

Directs the LTSSM to low power mode.

  • req_phypm[3]: L2 request
  • req_phypm[2]: L1 request
  • req_phypm[1]: L0s request
  • req_phypm[0]: exit any low power state to L0
req_phycfg[3:0]

Input

Configuration Space transition request bus:

  • req_phycfg[3]: Link retrain request. Retrain the link by writing 1b’1 in the retrain link bit in the Link Control register.
  • req_phycfg[2]: Recovery link request. Directs the LTSSM to the Recovery state.
  • req_phycfg[1]: Hot Reset request. Directs the LTSSM to the Hot Reset state.
  • req_phycfg[0]: Disable Link request. Directs the LTSSM to the Disable state.
vc0_tcmap_pld[7:1]

Input

Each bit corresponds to a Traffic Class. Bits[7:1] correspond to Traffic Class 7–Traffic Class 1. When a bit is set to 1, indicates that the corresponding Traffic Class maps to VC0. Traffic Class 0 always maps to Virtual Channel 0.

inh_dllp

Input

When asserted, all TLP and DLLP transmission requests are stalled at the TX Data Link to PHY interface, except for NAK and Power Management DLLPs.

inh_tx_tlp

Input

When asserted, all TLP transmission requests are stalled at the TX Transaction Layer to Data Link Layer interface. The Application Layer should assert this signal when requesting a low‑power state.

req_wake

Input

When asserted, requests the LTSSM to exit from a low‑power state.

link3_ctl[1]

Input

Link Control 3 register bit[1]: Link Equalization Request Interrupt Enable. When set to 1, enables the generation of an interrupt to indicate that the Link Equalization Request bit has been set.

link3_ctl[0]

Input

Link Control 3 register bit [0]. Perform Equalization. When set to 1, the downstream port must perform equalization.

Table 32.  Configuration Space Bypass Mode Output Signals Configuration Space Bypass signals that are driven from the hard Configuration Space in the Transaction Layer to the soft Configuration Space implemented in the Application Layer. The Configuration Space Bypass output signals have the prefix bypass_out_cfgbp_. All signals are synchronous to pld_clk.

Signal Name

Direction

Description

lane_err[7:0]

Output

When a bit is set to 1, indicates a lane error that is reported in the Lane Error Status register of the Secondary PCI Express Extended Capability structure. Bit 0 corresponds to lane 0.

link_equiz_req

Output

Reported as Bit 5 in the Link Status 2 register.

equiz_complete

Output

Reported as Bit 1 in the Link Status 2 register.

phase_3_successful

Output

Reported as Bit 4 in the Link Status 2 register.

phase_2_successful

Output

Reported as Bit 3 in the Link Status 2 register.

phase_1_successful

Output

Reported as Bit 2 in the Link Status 2 register.

current_deemph

Output

Current de-emphasis setting reported in the Link Status 2 register.

current_speed[1:0]

Output

Current link speed as reported in the Link Status register. The following encodings are defined:

  • 2'b01: Gen1
  • 2'b10: Gen2
  • 2'b11: Gen3
link_up

Output

When asserted indicates that the link is up and has exited the Configuration.Idle state.

link_train

Output

Reported as Bit 10 of the Link Status register. When asserted, indicates that the link is training.

l0state

Output

When asserted, indicates that the LTSSM is in the L0 state.

l0sstate

Output

When asserted, indicates that the LTSSM is in L0 or L0s state.

rx_val_pm[0]

Output

When asserted, indicates the Configuration Space has received a Power Management DLLP.

rx_typ_pm[2:0]

Output

Signals the type of received PM DLLP. Has the following values:

  • 000b: PM_Enter_L1
  • 001b: PM_Enter_L2L3
  • 011b: PM_AS_Request_L1
  • 100b: PM_Request_Ack
tx_ack_pm

Output

Pulse. Ack from TX Data Link in response to Power Management DLLP request tx_req_pm_pld.

ack_phypm[1:0]

Output

Acknowledge of transition to and from the low-power state when operations have been completed. The acknowledge bit mapping is the same as the request bit mapping.

  • Bit 0: rxelecidle deasserted or Training Sequence 1 (TS1) received, or rxvalid deasserted. Used for L1 exit.
  • Bit 1: RX Electrical Idle Ordered Set detected or TS1 received.
vc_status[0]

Output

When asserted, indicates that VC0 credits are initialized. When asserted, the VC Negotiation Pending bit of the VC Resource Status register can be cleared indicating that negotiation is complete.

rxfc_max

Output

When asserted, indicates the Transaction Layer has no high priority FC updates to send. High priority updates occur under the following conditions:

  1. The FC update timer expires because no new credits have become available in the timeout period since last update.
  2. The source has used all header credits from the last FC update and header credits have freed up.
  3. The last FC update did not give the source enough data credits to send a maximum payload TLP and data credits have since freed up.

Detects when TLP processing is complete for entry into low power state.

txfc_max

Output

When asserted, indicates that Transaction Layer has enough credits to send maximum payload TLPs of all types. Used for entry into low power state.

txbuf_emp

Output

When asserted, indicates there are no Application Layer TLPs pending for transmission in the Transaction Layer.

rpbuf_emp

Output

When asserted, indicates the replay buffer contains no TLPs.

dll_req

Output

When asserted, indicates that the Data Link Layer TX path has a pending request. Used to enable L0s entry or other low-power state. This is a level sensitive signal.

link_auto_bdw_status

Output

When asserted, indicates that the LTSSM detected an autonomous bandwidth change which is reported in the Link Status register.

link_bdw_mng_status

Output

When asserted, indicates that the LTSSM detected a non‑autonomous bandwidth change. Reported in the Link Status register.

rst_tx_margin_field

Output

When asserted, indicates that the Application Layer should reset the Transmit Margin field of the Link Control 2 register in the Application Layer’s soft Configuration Space.

rst_enter_comp_bit

Output

When asserted, indicates that the Application Layer should reset the Enter Compliance bit in the Link Control 2 register in the Application Layer’s soft Configuration Space.

rx_st_ecrcerr[3:0]

Output

Indicates which quad word on rx_st_data contains a TLP with an ECRC error. Only asserted during the cycle that in which the start of packet is asserted. Only valid only if internal ECRC error checking is enabled.

err_uncorr_internal

Output

When asserted, indicates an uncorrectable internal error was detected. This is a real‑time active high pulse.

err_corr_internal

Output

When asserted, indicates a corrected internal error (ECC) detected. This is a real‑time active high pulse.

err_tlrcvovf

Output

When asserted, indicates a receiver overflow error. This is a real‑time active high pulse.

txfc_err

Output

When asserted, indicates a TX Flow Control Protocol error. This is a real‑time active high pulse.

err_tlmalf

Output

When asserted, indicates a malformed TLP was detected and dropped. This is a real‑time active high pulse.

err_surpdwn_dll

Output

When asserted, indicates a surprise down error occurred. This is a real‑time active high pulse.

err_dllrcv

Output

When asserted, indicates a Data Link Protocol Error. This is a real‑time active high pulse.

err_dll_repnum

Output

When asserted, indicates a Replay_NUM rollover. This is a real‑time active high pulse.

err_dllreptim

Output

When asserted, indicates a Replay Timer Timeout. This is a real‑time active high pulse.

err_dllp_baddllp

Output

When asserted, indicates a bad DLLP was detected. This is a real‑time active high pulse.

err_dll_badtlp

Output

When asserted, indicates a bad TLP was detected. This is a real‑time active high pulse.

err_phy_tng

Output

When asserted, indicates a Link Training Error. This is a real‑time active high pulse.

err_phy_rcv

Output

When asserted, indicates a Receiver Error. This is a real‑time active high pulse.

root_err_reg_sts

Output

When asserted, indicates a a bit in the Root Error Status register is set. The Application Layer can read this register using the LMI. This bit clears when read.

corr_err_reg_sts

Output

When set to 1, indicates that a bit in Correctable Error Status register is set. The Application Layer can read this register using the LMI. This bit clears when read.

unc_err_reg_sts

Output

When set to 1, indicates that a bit in Uncorrectable Error Status register is set. The Application Layer can read this register using the LMI. This bit clears when read.

Level Two Title