Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683093
Date 5/03/2019
Public
Document Table of Contents

3.2. Generating the Qsys System

On the Qsys Generate menu, select Generate Testbench System. Specify the parameters listed in the following table.

Table 9.  Parameters to Specify on the Generation Tab in Qsys

Parameter

Value

Create testbench Qsys system

Standard, BFMs for standard Avalon interfaces

Create simulation model

Verilog

Allow mixed-language simulation

Turn this option off

Output Directory

Path

<working_dir>/top

Testbench

<working_dir>/top/testbench

  1. Click Generate to generate the simulation and testbench files.
  2. On the File menu, click Save.