Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

23.3.3. Hardware Options

The following options affect the hardware structure of the interval timer core. As a convenience, the Preset Configurations list offers several pre-defined hardware configurations, such as:
  • Simple periodic interrupt—This configuration is useful for systems that require only a periodic IRQ generator. The period is fixed and the timer cannot be stopped, but the IRQ can be disabled.
  • Full-featured—This configuration is useful for embedded processor systems that require a timer with variable period that can be started and stopped under processor control.
  • Watchdog—This configuration is useful for systems that require watchdog timer to reset the system in the event that the system has stopped responding. Refer to the Configuring the Timer as a Watchdog Timer section.

Register Options

Table 256.  Register Options
Option Description
Writeable period When this option is enabled, a host peripheral can change the count-down period by writing to the period registers. When disabled, the count-down period is fixed at the specified Timeout Period, and the period registers do not exist in hardware.
Readable snapshot When this option is enabled, a host peripheral can read a snapshot of the current count-down. When disabled, the status of the counter is detectable only via other indicators, such as the status register or the IRQ signal. In this case, the snap registers do not exist in hardware, and reading these registers produces an undefined value.
Start/Stop control bits When this option is enabled, a host peripheral can start and stop the timer by writing the START and STOP bits in the control register. When disabled, the timer runs continuously. When the System reset on timeout (watchdog) option is enabled, the START bit is also present, regardless of the Start/Stop control bits option.

Output Signal Options

Table 257.  Output Signal Options
Option Description
Timeout pulse
(1 clock wide) When this option is on, the core outputs a signal timeout_pulse. This signal pulses high for one clock cycle whenever the timer reaches zero. When this option is off, the timeout_pulse signal does not exist.
System reset on timeout (watchdog) When this option is on, the core’s Avalon® -MM agent port includes the resetrequest signal. This signal pulses high for one clock cycle whenever the timer reaches zero resulting in a system-wide reset. The internal timer is stopped at reset. Explicitly writing the START bit of the control register starts the timer.

When this option is off, the resetrequest signal does not exist.

Refer to the Configuring the Timer as a Watchdog Timer section.