Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

24.5.1. Software Control

The table below provides the register map for the status register. The layout of status register for the input and output interfaces is identical.
Table 269.  FIFO Status Register Memory Map
offset 31         24 23         16 15           8 7 6 5 4 3 2 1 0
base fill_level
base + 1   i_status
base + 2   event
base + 3   interrupt
enable
base + 4 almostfull
base + 5 almostempty
Table 270.   FIFO Status Field Descriptions
Field Type Description
fill_level RO The instantaneous fill level of the FIFO, provided in units of symbols for a FIFO with an Avalon® -ST FIFO and words for an Avalon® -MM FIFO.
i_status RO A 6-bit register that shows the FIFO’s instantaneous status. See Status Bit Field Description Table for the meaning of each bit field.
event RW1C A 6-bit register with exactly the same fields as i_status. When a bit in the i_status register is set, the same bit in the event register is set. The bit in the event register is only cleared when software writes a 1 to that bit.
interruptenable RW A 6-bit interrupt enable register with exactly the same fields as the event and i_status registers. When a bit in the event register transitions from a 0 to a 1, and the corresponding bit in interruptenable is set, the host Is interrupted.
almostfull RW A threshold level used for interrupts and status. Can be written by the Avalon® -MM status host at any time. The default threshold value for DCFIFO is Depth-4. The default threshold value for SCFIFO is Depth-1. The valid range of the threshold value is from 1 to the default. 1 is used when attempting to write a value smaller than 1. The default is used when attempting to write a value larger than the default.
almostempty RW A threshold level used for interrupts and status. Can be written by the Avalon® -MM status host at any time. The default threshold value for DCFIFO is 1. The default threshold value for SCFIFO is 1. The valid range of the threshold value is from 1 to the maximum allowable almostfull threshold. 1 is used when attempting to write a value smaller than 1. The maximum allowable is used when attempting to write a value larger than the maximum allowable.
Table 271.  Status Bit Field Descriptions
Bit(s) Name Description
0 FULL Has a value of 1 if the FIFO is currently full.
1 EMPTY Has a value of 1 if the FIFO is currently empty.
2 ALMOSTFULL Has a value of 1 if the fill level of the FIFO is equal or greater than the almostfull value.
3 ALMOSTEMPTY Has a value of 1 if the fill level of the FIFO is less or equal than the almostempty value.
4 OVERFLOW Is set to 1 for 1 cycle every time the FIFO overflows. The FIFO overflows when an Avalon® write host writes to a full FIFO. OVERFLOW is only valid when Allow backpressure is off.
5 UNDERFLOW Is set to 1 for 1 cycle every time the FIFO underflows. The FIFO underflows when an Avalon® read host reads from an empty FIFO. UNDERFLOW is only valid when Allow backpressure is off.

These fields are identical to those in the status register and are set at the same time; however, these fields are only cleared when software writes a one to clear (W1C). The event fields can be used to determine if a particular event has occurred.

Table 272.  Event Bit Field Descriptions
Bit(s) Name Description
0 E_FULL Has a value of 1 if the FIFO has been full and the bit has not been cleared by software.
1 E_EMPTY Has a value of 1 if the FIFO has been empty and the bit has not been cleared by software.
2 E_ALMOSTFULL Has a value of 1 if the fill level of the FIFO has been greater than the almostfull threshold value and the bit has not been cleared by software.
3 E_ALMOSTEMPTY Has a value of 1 if the fill level of the FIFO has been less than the almostempty value and the bit has not been cleared by software.
4 E_OVERFLOW Has a value of 1 if the FIFO has overflowed and the bit has not been cleared by software.
5 E_UNDERFLOW Has a value of 1 if the FIFO has underflowed and the bit has not been cleared by software.

The table below provides a mask for the six STATUS fields. When a bit in the event register transitions from a zero to a one, and the corresponding bit in the interruptenable register is set, the host is interrupted.

Table 273.  InterruptEnable Bit Field Descriptions
Bit(s) Name Description
0 IE_FULL Enables an interrupt if the FIFO is currently full.
1 IE_EMPTY Enables an interrupt if the FIFO is currently empty.
2 IE_ALMOSTFULL Enables an interrupt if the fill level of the FIFO is greater than the value of the almostfull register.
3 IE_ALMOSTEMPTY Enables an interrupt if the fill level of the FIFO is less than the value of the almostempty register.
4 IE_OVERFLOW Enables an interrupt if the FIFO overflows. The FIFO overflows when an Avalon® write host writes to a full FIFO.
5 IE_UNDERFLOW Enables an interrupt if the FIFO underflows. The FIFO underflows when an Avalon® read host reads from an empty FIFO.
6 ALL Enables all 6 status conditions to interrupt.

Macros to access all of the registers are defined in altera_avalon_fifo_regs.h. For example, this file includes the following macros to access the status register.

#define ALTERA_AVALON_FIFO_LEVEL_REG         0
#define ALTERA_AVALON_FIFO_STATUS_REG        1
#define ALTERA_AVALON_FIFO_EVENT_REG         2
#define ALTERA_AVALON_FIFO_IENABLE_REG       3
#define ALTERA_AVALON_FIFO_ALMOSTFULL_REG    4
#define ALTERA_AVALON_FIFO_ALMOSTEMPTY_REG   5

For a complete list of predefined macros and utilities to access the on-chip FIFO hardware, see:
  • <install_dir>\quartus\sopc_builder\components\altera_avalon_fifo\HAL\inc\
alatera_avalon_fifo.h
  • <install_dir>\quartus\sopc_builder\components\altera_avalon_fifo\HAL\inc\
alatera_avalon_fifo_util.h.