Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

55.2.5. Transmitter Logic

The Lightweight UART transmitter consists of a 7-, 8-, or 9-bit width of TXFIFO and a corresponding 7-, 8-, or 9-bit transmit shift register. The TXFIFO can be implemented either in register with configurable depth or a fixed depth that is able to fully utilize a single memory block.

Avalon® memory-mapped host peripherals write the TXFIFO via the Avalon® memory-mapped agent port. The transmit shift register is loaded from the TXFIFO automatically if a serial transmit shift operation is not currently in progress. The transmit shift register directly feeds the TXD output. Data is shifted out to TXD LSB first.

These two registers provide double buffering. A host peripheral can write new value into the TXFIFO while the previously written character is being shifted out.

The host peripheral can monitor the status of the transmitter by reading the status registers transmit ready (TRDY), transmit data empty (TMT), and TXFIFO overrun error (TOE) bits. You are only allowed to write data to TXFIFO if the TRDY bits is HIGH, which indicates that TXFIFO is not full. Writing to TXFIFO if the TRDY bits is LOW will hit into the TXFIFO overrun error. If the overrun error occurs, TXFIFO no longer accepts subsequent write data, causing the data to be missing. The existing data that has been stored in TXFIFO will not be overwritten. The TOE bits are set and remain HIGH. The TOE bits can only be cleared by writing to the status register.

The TXFIFO filled level can be monitored by reading the value of the TXFIFO_LVL register. Note that if TXFIFO is full, the TXFIFO level rolls over to 0. Thus, the value 0 of TXFIFO_LVL can indicate either that the TXFIFO is full (that is, when the status registers transmit ready (TRDY) bit is LOW) or TXFIFO is empty.

To break data transmission, you can set the transmit break bit (TRBK) of the control register HIGH to hold TXD stream LOW. During the break condition, the transmit data that are left in TXFIFO and transmit shift register will be flushed out.

The transmitter logic automatically inserts the correct number of start, stop, and parity bits in the serial TXD data stream as required by the RS-232 specification.