7. Document Revision History for the 25G Ethernet Intel® Stratix® 10...

25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683252

Date 6/18/2020

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7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

Document Version	Intel® Quartus® Prime Version	IP Version	Changes
2020.06.18	19.2	19.2.0	Updated the following Figures: Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) Without the IEEE 1588v2 Feature Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) with the IEEE 1588v2 Feature Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) Without the IEEE 1588v2 Feature Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) with the IEEE 1588v2 Feature Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) Without the IEEE 1588v2 Feature Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) with the IEEE 1588v2 Feature Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) Without the IEEE 1588v2 Feature Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) with the IEEE 1588v2 Feature Block Diagram—25G Ethernet Multi-Channel Design Example (MAC+PCS+PMA Core Variant) Updated the document for latest Intel® branding standards.
2020.04.13	19.2	19.2.0	Added new topic—Using Transceiver Toolkit on H-Tile Production Device.
2020.02.14	19.2	19.2.0	Updated the procedure steps in the Changing Target Device in Hardware Design Example section.
2019.12.13	19.2	19.2.0	Updated the procedure steps in the Changing Target Device in Hardware Design Example section.
2019.08.29	19.2	19.2.0	Updated the instruction for the ModelSim* simulator in Table: Steps to Simulate the Testbench.
2019.07.01	19.2	19.2.0	Added new topic—Changing Target Device in Hardware Design Example. Updated references to Intel® Stratix® 10 L-Tile GX Transceiver Signal Integrity Development Kit (OPN: 1SX280LU2F50E2VG) as Intel® Stratix® 10 GX Signal Integrity L-Tile (Production) Development Kit (OPN: 1SX280LU2F50E1VG). Updated the Generating the Design Example topic to add a note to Step 8. Updated Figure: Example Design Tab in the 25G Ethernet Intel® FPGA IP Parameter Editor. Updated the Hardware and Software Requirements topics for all design example chapters.

Document Version	Intel® Quartus® Prime Version	Changes
2019.05.10	19.1	Renamed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME). Updated the hardware testing steps for the following topics: Test Procedure—Design Example Without the IEEE 1588v2 Feature for 10G/25G Ethernet single-channel design example. Test Procedure—Design Example with the IEEE 1588v2 Feature for 10G/25G Ethernet single-channel design example. Test Procedure—Design Example With and Without the IEEE 1588v2 Feature for 25G Ethernet single-channel design example. Test Procedure for 25G Ethernet multi-channel design example. Updated the following Figures: Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) Without the IEEE 1588v2 Feature Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) with the IEEE 1588v2 Feature Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) Without the IEEE 1588v2 Feature Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) with the IEEE 1588v2 Feature Updated Table: Hardware Design Example Register Map for 25G Ethernet Intel® FPGA IP Core for Intel® Stratix® 10 Devices to include reconfiguration registers (0x04000-0x37FFF). Updated the note section in the Design Example Registers topic. Made editorial updates throughout the document.
2019.01.07	18.1	Updated the Generating the Design Example topic to correct target development kit in Step 8 from Stratix 10 GX FPGA Development Kit to Intel Stratix 10 L-Tile GX Transceiver Signal Integrity Development Kit. Updated Figure: Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) with the IEEE 1588v2 Feature. Added a note to Design Example Registers topic.
2018.10.03	18.1	Updated Table: Parameters in the Example Design Tab to update the description for Select Board. Updated the Hardware and Software Requirements topics for all design example chapters. Updated the Design Components topics for all design example chapters. Added new Figures: Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) Without the IEEE 1588v2 Feature Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) Without the IEEE 1588v2 Feature Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) Without the IEEE 1588v2 Feature Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS Core Variant) with the IEEE 1588v2 Feature Updated Figures: Example Design Tab in the 25G Ethernet Intel FPGA IP Parameter Editor Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) with the IEEE 1588v2 Feature Block Diagram—25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant) Without the IEEE 1588v2 Feature Block Diagram—25G Ethernet Multi-Channel Design Example (MAC+PCS+PMA Core Variant) Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA) Without the IEEE 1588v2 Feature Block Diagram—10G/25G Ethernet Single-Channel Design Example (MAC+PCS+PMA) with the IEEE 1588v2 Feature Removed Figure: Sample Simulation Output for Design Example with the IEEE 1588v2 Feature (Part 1 of 2) and Sample Simulation Output for Design Example with the IEEE 1588v2 Feature (Part 2 of 2). Updated the simulation sample output of the Test Case—Design Example with the IEEE 1588v2 Feature topic for 25G Ethernet Single-Channel design example. Updated the simulation sample output of the Test Case—Design Example with the IEEE 1588v2 Feature topic for the 10G/25G Ethernet design example. Restructured descriptions for Features topics for all design example chapters. Streamlined the contents and document organization.
2018.06.25	18.0	Initial release.