25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683252
Date 6/18/2020
Public
Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel® FPGA IP Quick Start Guide 2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices 5. 25G Ethernet Intel® FPGA IP Design Example References 6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. 25G Ethernet Intel® FPGA IP Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench x
1.3.1. Procedure
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure
1.5. Changing Target Device in Hardware Design Example x
1.5.1. Procedure
1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware x
1.6.1. Procedure
2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 2.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
2.6. Hardware Testing x
2.6.1. Test Procedure—Design Example Without the IEEE 1588v2 Feature 2.6.2. Test Procedure—Design Example with the IEEE 1588v2 Feature
3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Compilation 3.6. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
3.6. Hardware Testing x
3.6.1. Test Procedure—Design Example With and Without the IEEE 1588v2 Feature
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Compilation 4.6. Hardware Testing
4.3. Functional Description x
4.3.1. Design Components
4.4. Simulation x
4.4.1. Testbench 4.4.2. Simulation Design Example Components 4.4.3. Test Case
4.6. Hardware Testing x
4.6.1. Test Procedure
5. 25G Ethernet Intel® FPGA IP Design Example References x
5.1. Design Example Interface Signals 5.2. Design Example Registers 5.3. Using Transceiver Toolkit on H-Tile Production Device
1. 25G Ethernet Intel® FPGA IP Quick Start Guide
2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices
5. 25G Ethernet Intel® FPGA IP Design Example References
6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.6.1. Test Procedure—Design Example Without the IEEE 1588v2 Feature

Follow these steps to test the design examples in hardware using PMA serial loopback:
Note: The design example starts with default data rate of 25G.
  1. Perform data rate switching to 10G:
    1. In Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources & Probes Editor tool to open the default source and probe GUI.
    2. Set the source bit[1] in source and probe to 1.
  2. Perform data rate switching to 25G:
    1. In Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources & Probes Editor tool to open the default source and probe GUI.
    2. Set the source bit[1] in source and probe to 0.
  3. Perform system reset release after executing the data rate reconfiguration:
    1. Click Tools > In-System Sources & Probes Editor tool for the default Source and Probe GUI.
    2. Toggle the system reset signal (Source[0]) from 0 to 1 to apply the reset and return the system reset signal back to 0 to release the system from the reset state.
    3. Monitor the Probe signals and ensure that the status is valid.
  4. Run the following commands in the system console to start the serial loopback test:
    Table 7.  Command Parameters
    Parameter Description Example Usage
    chkphy_status <link num> Displays the clock frequencies and PHY lock status. % chkphy_status 0 # Check status of link 0
    chkmac_stats <link num> Displays the values in the MAC statistics counters. % chkmac_stats 1 # Checks mac statistics counter of link 1
    clear_all_stats <link num> Clears the IP core statistics counters. % clear_all_stats 1 # Clears statistics counter of link 1
    start_gen <link num> Starts the packet generator. % start_gen 1 # Begin packet generation on link 1
    stop_gen <link num> Stops the packet generator. % stop_gen 1 # Stop packet generation on link 1
    loop_on <link num> Turns on internal serial loopback. % loop_on 2 # Turn on internal loopback on link 2
    loop_off <link num> Turns off internal serial loopback. % loop_off 2 # Turn off internal loopback on link 2
    reg_read <addr> Returns the IP core register value at <addr>. % reg_read 0x302 # Read IP CSR register at address 302 of link 0

    % reg_read 0x4542 # Read transceiver reconfiguration register at address 4542 of link 0

    reg_write <addr> <data> Writes <data> to the IP core register at address <addr>. % reg_write 0x30301 0x1 # Write 0x1 to IP CSR scratch register at address 301 of link 3

    % reg_write 0x34542 0x0 # Write 0x0 to transceiver reconfiguration register at address 4542 of link 3

    Note:
    1. For single-channel design, <link num> is always 0.
    2. For multi-channel design, <link num> is the channel number. The valid channel number range is 0 to 3.
    1. Type loop_on <link num> to turn on the internal serial loopback mode.
    2. Type chkphy_status <link num> to check the status of the PHY. The TXCLK, RXCLK, and RX status should have the same values shown below for a stable link:
      Figure 11. System Console Example Printout
    3. Type clear_all_stats <link num> to clear TX and RX statistics registers.
    4. Type start_gen <link num> to begin packet generation.
    5. Type stop_gen <link num> to stop packet generation.
    6. Type chkmac_stats <link num> to read the TX and RX statistics counters. Make sure that:
      1. The transmitted packet frames match the received packet frames.
      2. No error frames are received.
    7. Type loop_off <link num> to turn off the internal serial loopback.
    Note: The above configuration is applied to the default 25G mode for the first time.
Figure 12. Sample Test Output—TX and RX Statistics Counters
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