Battery Management System Reference Design

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ID 683279
Date 4/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Battery Management System Reference Design
1. Battery Management System Reference Design x
1.1. BMS Reference Design Features 1.2. BMS Reference Design Getting Started 1.3. BMS Reference Design Functional Description 1.4. BMS Reference Design FPGA Resource Usage 1.5. BMS Reference Design Benchmarking 1.6. Acknowledgements for the BMS Reference Design
1.2. BMS Reference Design Getting Started x
1.2.1. BMS Reference Design Software Requirements 1.2.2. BMS Reference Design Hardware Requirements 1.2.3. Downloading and Installing the BMS Reference Design 1.2.4. Setting Up the MAX 10 Development Board 1.2.5. Compiling the FPGA Hardware Design for the BMS Reference Design 1.2.6. Compiling the Nios Software for the BMS Reference Design 1.2.7. Programming the BMS Reference Design Hardware onto the Device 1.2.8. Downloading the BMS Reference Design Nios II Software to the Device 1.2.9. MATLAB Simulink Top-Level Design for the BMS Reference Design 1.2.10. Running the BMS Reference Design in a System-in-the-Loop Simulation
1.3. BMS Reference Design Functional Description x
1.3.1. BMS Reference Design Car Model 1.3.2. BMS Reference Design Battery Model 1.3.3. BMS Reference Design DEKF Technique 1.3.4. BMS Reference Design Hardware Implementation
1.3.4. BMS Reference Design Hardware Implementation x
1.3.4.1. BMS Reference Design Matrix Processor 1.3.4.2. BMS Reference Design uCode Controller Interface 1.3.4.3. BMS Reference Design DEKF IP (Design C)
1. Battery Management System Reference Design

1.3.4. BMS Reference Design Hardware Implementation

The reference design includes three different designs to implement the DEKF algorithm:

  • Design A,which has a Nios II processor with floating-point acceleration
  • Design B, which has a Nios II processor with floating-point acceleration and floating-point matrix processor
  • Design C, which has a Nios II processor and DEKF algorithm implemented in dedicated floating-point IP

The reference design creates the dedicated floating-point IP using Altera’s DSP Builder advanced blockset. In each design, every functional component takes charge of different tasks, including system-in-the-loop communication with MATLAB Simulink, cell link list management, DEKF calculation. In the three designs, the Nios processor II controls the system-in-the-loop and cell link tasks. In design B, both the Nios II processor and matrix processor perform the DEKF calculation, and the matrix processor processes most of the matrix calculations. Finally, in design C, DSP Builder IP processes all DEKF calculations.

To switch between different implementation methods, modify this line in source file

 \software
\bms_soc_microc
\soc_kalman.h: 
// 0 - Nios2 only 
// 1 - Matrix processor 
// 2 - DSP Builder IP 
#define ACC 1
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