AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

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ID 683393
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Intel Agilex® 7 Device Family PDN Design Summary 9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Intel Agilex® 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Intel Agilex® 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Intel Agilex® 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Intel Agilex® 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Intel Agilex® 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Intel Agilex® 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Intel Agilex® 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Intel Agilex® 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Intel Agilex® 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Intel Agilex® 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Intel Agilex® 7 Device Family PDN Design Summary
9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

2.3.3. Power Nets and Transient Specifications

Rail transient provided in the Table 11 is used to design and simulate the board level. Choose the recommended load slew rates and step load at FPGA package ball below for PCB-level PDN system simulations and design. Table 11 shows the maximum tolerable step load at FPGA package pin. The recommended step load in Table 11 is connected to FPGA package ball along with the PCB post-layout model (with decoupling capacitors and voltage regulator model excluding package and silicon/die model) in an EDA tool for time domain simulation to meet rail tolerance of respective power net in Table 10 at FPGA package ball.

Table 11 shows for the recommended step load at package ball and step load’s slew rate.

Note: The step load suggested in Table 11 is for a normal application and worst case operation in FPGA and tiles. Step load can also be scaled if the dynamic current of the target power rail in PTC is smaller than the step load in Table 11.
Table 11.   Intel Agilex® 7 Device Family Transient and Step Load Specifications at Package Pin
Package Power Rails At Package Balls (Step Load) DI/dt at Package Balls (for Board Design)-Slew Rate Notes
DI (A)-Step Load DI/dt (A/µs)-Slew Rate
VCC/VCCP Core: AGF006/AGF008 4 20 The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.
VCC/VCCP Core: AGF012/AGF014 17 200 The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.
VCC/VCCP Core: AGF012/AGF014 (low power scenario) 12 141 Low power scenario case, maximum current at 70 A.
VCC/VCCP Core: AGF019/AGF023 and AGI019/AGI023 30.5 305 The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.
VCC/VCCP Core: AGF027/AGF022 and AGI027/AGI022 32.5 325 The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.
VCC/VCCP Core: AGI035/AGI040 7 269 The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.
VCC/VCCP Core: AGI041 21 420 The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.
VCC/VCCP Core: AGM039/AGM032 (R47A) 23 742 The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.
VCC/VCCP Core: AGM039/AGM032 (R31B) 6 111 The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.
VCCPT 2.4 12 —
VCCPT (low power scenario) 0.22 1.1 Low power scenario case, maximum current at 0.8 A.
VCCIO_PIO 0.645 10.8 Current specification is per I/O bank. Each I/O bank consists of 96 x I/Os. More I/O banks can join the same voltage regulator but current specification stays per I/O bank.
VCCH 1.12 4.8 Step current at package ball per each AIB Bridge. The number of AIB Bridge is calculated based on number of tiles in package.
VCCRT_GXE 0.88 35.2 Per E-Tile
VCCRT_GXE (low power scenario) 0.44 5.86 Per 2 quads of E-Tile, low power scenario case, maximum current at 3 A.
VCCRTPLL_GXE 0.3 6 Per E-Tile
VCC_HSSI_GXP 1.6 20 Per P-Tile
VCC_HSSI_GXP (low power scenario) 1.0 10 Per P-Tile, low power scenario case, maximum current at 3.5 A.
VCCRT_GXP 1.56 14.85 Slowest step load but largest current amplitude. Per P-Tile.
VCCRT_GXP (low power scenario) 0.3 6 Per 2 quads of P-Tile, low power scenario case, maximum current at 1.5 A.
VCCH_GXP 0.37 50 Per P-Tile
VCCH_GXP (low power scenario) 0.2 50 Per P-Tile, low power scenario case, maximum current at 0.7 A.
VCC_HSSI_GXF 0.825 30.55 Per F-Tile
VCCERT_FGT_GXF 0.228 22.8 Per single FGT—F-Tile channel
0.935 1.33 For 8 x FGT—F-Tile channels
1.87 1.24 For 16 x FGT—F-Tile channels
VCCH_FGT_GXF 0.031 31 Per single FGT—F-Tile channel
0.18 0.26 For 8 x FGT—F-Tile channels
0.37 0.25 For 16 x FGT—F-Tile channels
VCCERT2_FHT_GXF 0.03 0.49 Per single FHT—F-Tile channel
0.128 0.43 For 4 x FHT—F-Tile channels
VCCERT1_FHT_GXF 0.207 3.04 Per single FHT—F-Tile channel
0.785 2.62 For 4 x FHT—F-Tile channels
VCCEHT_FHT_GXF 0.022 0.35 Per single FHT—F-Tile channel
0.064 0.21 For 4 x FHT—F-Tile channels
VCC_HSSI_GXR 1.585 52.83 Per R-Tile
VCCRT_GXR 2.47 6.58
VCCH_GXR 0.026 12.56

You must also notice the following:

  1. Step current at package pin is only provided for critical power rails due to either having high current/power profile at die or being highly sensitive. Intel® recommends you to do transient/time domain PDN simulation by using this step load for these critical power rails in Table 11 to ensure you will meet the voltage specification at package pin. If the voltage specification is not met at package pin, decoupling capacitors must be adjusted.
  2. Intel® do not provide step current for other power rails not mentioned in Table 11. Those power rails are called non-critical power rail due to having less sensitivity or low current profile/power consumption at silicon. Intel® do not recommend time domain PDN analysis for non-critical power rails. Non-critical power rails PDN design suggested in this application note is guaranteed.
  3. Intel® recommends you to perform DC IR drop analysis for all power rails.
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