AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

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ID 683393
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Intel Agilex® 7 Device Family PDN Design Summary 9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Intel Agilex® 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Intel Agilex® 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Intel Agilex® 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Intel Agilex® 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Intel Agilex® 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Intel Agilex® 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Intel Agilex® 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Intel Agilex® 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Intel Agilex® 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Intel Agilex® 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Intel Agilex® 7 Device Family PDN Design Summary
9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

2.4.5. Intel Agilex® 7 R-Tile Board-Level Decoupling Capacitors Summary

Table 16.   Intel Agilex® 7 R-Tile Decoupling Capacitors Summary per Tile
Intel Agilex® 7 PTC Rail Name Bottom-side Capacitors FPGA Periphery Capacitors Notes
Thick PCB (≥65 mil thickness) Thin PCB (≤65 mil thickness) Thick PCB (≥65 mil thickness) Thin PCB (≤65 mil thickness)
VCC_HSSI_GXR 2x 10uF 0402 2x 47uF 0805 Per each R-Tile
VCCE_PLL_GXR 1x 4.7uF 0201 N/A Per each R-Tile
VCCE_DTS_GXR
VCCRT_GXR 4x 10uF 0402 2x 47uF 0805

Per each R-Tile.
4x 10uF 0402 2x 220uF 1206 + 3x 100uF 0805 Per each R-Tile: If LDO voltage regulator is used for this power rail.
VCCH_GXR 1x 10uF 0402 1x 47uF 0805

Per each R-Tile.
VCCED_GXR 1x 10uF 0402 1x 47uF 0805 Per each R-Tile
VCCCLK_GXR 2x 10uF 0402 N/A Per each R-Tile
VCCHFUSE_GXR 2x 10uF 0402 N/A Per each R-Tile

The capacitors listed in the tables above have been validated on the Intel® development kits and should be used as a reference only. You have the option to choose other capacitors according to specific applications, package size used, temperature range, form factor, and rated voltage, as long as the specifications stated above are met and the LC filter works well. Intel® recommends you to run the simulation to ensure there is no further changes.

This recommended decoupling capacitors solution has been verified along with the use of the recommended switching voltage regulator or LDO in the example power trees. You can use other switching voltage regulators or LDOs as long as you meet the PCB power rail tolerance specification in Table 10. Intel® recommends performing the PCB time domain simulation by using the step load in Table 11 for critical power rails. Intel® do not support customers' PCB PDN time domain simulation. It is your responsibility to use the data and specifications in this document along with the simulation guidance in the Board Power Delivery Network Simulations chapter to perform the PDN time domain simulation.

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