Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

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ID 683588
Date 12/01/2017
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Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition) x
Step 1: Open the Project and Compile Step 2: Specify Clock Constraints Step 3: View Clock Timing Analysis Step 4: Declare False Paths Step 5: View Post-Fit Timing Results Step 6: Specify Input and Output Delay Constraints Step 7: Report Clocks and Top Failing Paths Document Revision History
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)

Step 1: Open the Project and Compile

This tutorial uses a simple fir_filter design to demonstrate the Intel® Quartus® Prime Timing Analyzer.

The Intel® Quartus® Prime software installation includes the sample fir_filter project in the quartus/qdesigns/fir_filter/ directory. The following steps describe opening the example project and running initial compilation to elaborate the design hierarchy, synthesize logic, and generate a node netlist for application of constraints.

  1. Launch the Intel® Quartus® Prime Pro Edition software.
  2. To open the example design project, click File > Open Project, and open the quartus/qdesigns/fir_filter/fir_filter.qpf project file.
  3. To view the top-level design schematic, click Open on the Tasks pane, select the filtref.bdf file, and click Open. The filtref.bdf schematic appears in the Block Editor.
  4. Perform one of the following from the Compilation Dashboard. (To display the Dashboard if closed, click Processing > Compilation Dashboard).
    • To run the Fitter, click Fitter (or any Fitter stage) on the Compilation Dashboard.
    • To run a full compilation, click Compile Design on the Compilation Dashboard.
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