Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

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Date 12/01/2017
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Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition) x
Step 1: Open the Project and Compile Step 2: Specify Clock Constraints Step 3: View Clock Timing Analysis Step 4: Declare False Paths Step 5: View Post-Fit Timing Results Step 6: Specify Input and Output Delay Constraints Step 7: Report Clocks and Top Failing Paths Document Revision History
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)

Step 7: Report Clocks and Top Failing Paths

After constraining all paths, follow these steps to report top failing timing paths:
  1. Under Custom Reports, double-click Report Timing, and then specify the following options. Retain the default settings for the other options.
    Option Setting
    To clock clk
    Targets To: acc:inst3|result*
    Analysis type Setup
    Report number of paths 10
    Tcl command report_timing -setup -npaths 10 -detail full_path -panel_name {Report Timing} -multi_corner
  2. Click Report Timing. The Slow 900mV 100C Model report shows the 10 worst paths between the clk and acc:inst3|result nodes.
  3. To report the top failing paths in the design, double-click Report Top Failing Paths in the Macros reports.

    Continue optimizing the design and running timing analysis until the design meets all requirements.

Level Two Title