AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

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ID 683624
Date 1/29/2020
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Document Table of Contents
Document Table of Contents x
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission x
1.1. PCB Material Selection 1.2. Stackup Design 1.3. Channel Design 1.4. Summary 1.5. Document Revision History for the AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1.1. PCB Material Selection x
1.1.1. Loss Tangent and Dissipation Factor 1.1.2. Dielectric Constant 1.1.3. Fiberglass Weave 1.1.4. Copper Surface Roughness
1.3. Channel Design x
1.3.1. BGA Channel Breakout 1.3.2. Channel Routing Design 1.3.3. Edge Coupling 1.3.4. Broadside Coupling 1.3.5. Transparent Via Design 1.3.6. Blocking Cap Optimization 1.3.7. Connectors Optimization
1.3.2. Channel Routing Design x
1.3.2.1. Trace Width Selection 1.3.2.2. Loose vs. Tight Coupled Traces 1.3.2.3. Crosstalk Control
1.4. Summary x
1.4.1. PCB Material Selection 1.4.2. Stackup Design 1.4.3. Channel Design 1.4.4. References
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

1.3.7. Connectors Optimization

Another component commonly found in the path of transceiver channels are backplane connectors and optical interface modules such as SFP+, XFP, and CFP2 among many others. For these components, the manufacturer may have specific design recommendations for the best connector performance, and the designer should follow those recommendations. If no recommendation is provided by the manufacturer, perform simulations to determine the best layout optimization. However, because most backplane and optical connector systems use press-fit through-hole via or surface mount pad technology respectively, the concept for optimization is very similar to that done for transparent via design and DC blocking capacitor compensation. The impact of impedance mismatch limits performance. For these cases, you can use the same methodology to optimize both the vias and surface mount pads in the connectors to better match the connector impedance to the 100-Ω trace impedance.

Figure 28.  Example Backplane Connector Layout

Example Backplane and XFP Connector Layout

Figure 29.  Example XFP Optical Module Connector Layout

Example XFP optical module connector layout

Notice that the via and surface mount pads show evidence of optimization such as increased via anti-pad size and plane cut-outs underneath the surface mount pads.

Note: Use manufacturer layout recommendations for connectors if available. In the absence of any specific manufacturer recommendations, designers can apply the transparent via optimization and DC blocking capacitor compensation technique to connector systems that use through-hole via and surface mount pad technologies, respectively.
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