AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

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ID 683624
Date 1/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission x
1.1. PCB Material Selection 1.2. Stackup Design 1.3. Channel Design 1.4. Summary 1.5. Document Revision History for the AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1.1. PCB Material Selection x
1.1.1. Loss Tangent and Dissipation Factor 1.1.2. Dielectric Constant 1.1.3. Fiberglass Weave 1.1.4. Copper Surface Roughness
1.3. Channel Design x
1.3.1. BGA Channel Breakout 1.3.2. Channel Routing Design 1.3.3. Edge Coupling 1.3.4. Broadside Coupling 1.3.5. Transparent Via Design 1.3.6. Blocking Cap Optimization 1.3.7. Connectors Optimization
1.3.2. Channel Routing Design x
1.3.2.1. Trace Width Selection 1.3.2.2. Loose vs. Tight Coupled Traces 1.3.2.3. Crosstalk Control
1.4. Summary x
1.4.1. PCB Material Selection 1.4.2. Stackup Design 1.4.3. Channel Design 1.4.4. References
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

1.5. Document Revision History for the AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

Document Version Changes
2020.01.29 Fixed the formatting and an error in the "Copper Roughness Approximation Equations" in the Dielectric Constant topic.
2017.05.08 Rebranded as Intel.
2017.02.02
  • Changed the KSR equation and added clarification to the Ra note in the Copper Roughness Approximation Equations figure.
  • Clarified the units of measure for WpN in the "DC Blocking Capacitor Compensation" figure.
2013.02.15 Initial release
Level Two Title