Putting Altera MAX Series in Hibernation Mode Using User Flash Memory

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ID 683668
Date 1/14/2016
Public
Document Table of Contents
Document Table of Contents x
1. Putting Altera MAX Series in Hibernation Mode Using User Flash Memory
1. Putting Altera MAX Series in Hibernation Mode Using User Flash Memory x
1.1. Design Example Description 1.2. External Hardware Circuitry 1.3. Design in the MAX II Device 1.4. Design in the MAX 10 Device 1.5. Document Revision History
1.3. Design in the MAX II Device x
1.3.1. 4-Bit Binary Up-Counter 1.3.2. Data Controller 1.3.3. Timer 1.3.4. User Flash Memory Instantiation Module 1.3.5. User Flash Memory Data Save and Retrieval Method
1.4. Design in the MAX 10 Device x
1.4.1. 4-Bit Binary Up-Counter 1.4.2. 16-Bit Binary Slow Counter 1.4.3. Main Controller 1.4.4. Random Start Block
1. Putting Altera MAX Series in Hibernation Mode Using User Flash Memory

1.4.3. Main Controller

The main controller is the heart of the design. The main controller instantiates the UFM which has an Avalon® Memory-Mapped (MM) Slave interface and controls all of the reading and writing to the UFM.

At power-up, the random start block issues a POR cycle and then sends a signal to the main data controller to read the UFM stored counter value at a static address and sends it to the 4-bit binary up-counter.

After the power-up fetch process completes, the main controller sits idle until the Reset signal is asserted or when it receives a signal from the 16-bit binary slow counter to initiate the power-down sequence.

When the main controller receives the power-down signal from the 16-bit binary slow counter, the main controller reads the current 4-bit binary up-counter value, removes the write protection of the UFM, writes the 4-bit binary up-counter value to the static address hard-coded in the design, turns back on the write protection for the UFM, and then sends the pwr_dwn_ready signal out of the device, which shuts off the power supply to the MAX 10 device.

Level Two Title