Intel® Stratix® 10 GX FPGA Development Kit User Guide

Download PDF
ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.6.7. DisplayPort

The Intel® Stratix® 10 GX FPGA development board includes a Mini-DisplayPort connector.
Table 26.  Mini-DisplayPort Schematic Signal Names and Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard Description
J12.4 DP_3p3V_CONFIG1 AN26 1.8V –
J12.6 DP_3p3V_CONFIG2 AP26 1.8V –
J12.2 DP_3p3V_HOT_PLUG AU27 1.8V Hot plug detect
J12.18 DP_AUX_CN AN25 LVDS Auxiliary channel (negative)
J12.16 DP_AUX_CP AP25 LVDS Auxiliary channel (positive)
J12.5 DP_ML_LANE_CN0 AK48 1.4V PCML Lane 0 (negative)
J12.11 DP_ML_LANE_CN1 AL46 1.4V PCML Lane 1 (negative)
J12.17 DP_ML_LANE_CN2 AH48 1.4V PCML Lane 2 (negative)
J12.12 DP_ML_LANE_CN3 AJ46 1.4V PCML Lane 3 (negative)
J12.3 DP_ML_LANE_CP0 AK49 1.4V PCML Lane 0 (positive)
J12.9 DP_ML_LANE_CP1 AL47 1.4V PCML Lane 1 (positive)
J12.15 DP_ML_LANE_CP2 AH49 1.4V PCML Lane 2 (positive)
J12.10 DP_ML_LANE_CP3 AJ47 1.4V PCML Lane 3 (positive)
Level Two Title