Visible to Intel only — GUID: sss1394416834269
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1.1. Logic Array Block
1.2. Embedded Memory
1.3. Embedded Multiplier
1.4. Clocking and PLL
1.5. General Purpose I/O
1.6. High-Speed LVDS I/O
1.7. External Memory Interface
1.8. Analog to Digital Converter
1.9. Configuration Schemes
1.10. User Flash Memory
1.11. Power Management
1.12. Document Revision History for Intel® MAX® 10 FPGA Device Architecture
Visible to Intel only — GUID: sss1394416834269
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1.9. Configuration Schemes
Figure 30. High-Level Overview of JTAG Configuration and Internal Configuration for Intel® MAX® 10 Devices
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