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1.1. Logic Array Block
1.2. Embedded Memory
1.3. Embedded Multiplier
1.4. Clocking and PLL
1.5. General Purpose I/O
1.6. High-Speed LVDS I/O
1.7. External Memory Interface
1.8. Analog to Digital Converter
1.9. Configuration Schemes
1.10. User Flash Memory
1.11. Power Management
1.12. Document Revision History for Intel® MAX® 10 FPGA Device Architecture
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1.5.1. Intel® MAX® 10 I/O Banks Architecture
The I/O elements are located in a group of four modules per I/O bank:
- High speed DDR3 I/O banks—supports various I/O standards and protocols including DDR3 but not the 1.8 V LVDS I/O standard. These I/O banks are available only on the right side of the device.
- High speed I/O banks—supports various I/O standards and protocols except DDR3. These I/O banks are available on the top, left, and bottom sides of the device.
- Low speed I/O banks—lower speeds I/O banks that are located at the top left side of the device.
For more information about I/O pins support, refer to the pinout files for your device.