Embedded Peripherals IP User Guide

ID 683130
Date 8/15/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

18.2. Functional Description

As shown below, the EPCS/EPCQA device's memory can be thought of as two separate regions:

  • FPGA configuration memory—FPGA configuration data is stored in this region.
  • General-purpose memory—If the FPGA configuration data does not fill up the entire EPCS/EPCQA device, any left-over space can be used for general-purpose data and system startup code.
Figure 65.  Nios® II System Integrating an EPCS/EPCQA Serial Flash Controller Core
  • By virtue of the HAL generic device model for flash devices, accessing the EPCS/EPCQA device using the HAL API is the same as accessing any flash memory. The EPCS/EPCQA device has a special-purpose hardware interface, so Nios II programs must read and write the EPCS/EPCQA memory using the provided HAL flash drivers.

The EPCS/EPCQA serial flash controller core contains an on-chip memory for storing a boot-loader program. When used in conjunction with Cyclone® and Cyclone®  II devices, the core requires 512 bytes of boot-loader ROM. For Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, Stratix® II, and newer device families in the Stratix® series, the core requires 1 KByte of boot-loader ROM. The Nios® II processor can be configured to boot from the EPCS/EPCQA serial flash controller core. To do so, set the Nios® II reset address to the base address of the EPCS/EPCQA serial flash controller core. In this case, after reset the CPU first executes code from the boot-loader ROM, which copies data from the EPCS/EPCQA general-purpose memory region into a RAM. Then, program control transfers to the RAM. The Nios® II IDE provides facilities to compile a program for storage in the EPCS/EPCQA device, and create a programming file to program into the EPCS/EPCQA device.

For more information, refer to the Nios II Flash Programmer User Guide.

If you program the EPCS/EPCQA device using the Intel® Quartus® Prime Programmer, all previous content is erased. To program the EPCS/EPCQA device with a combination of FPGA configuration data and Nios II program data, use the Nios® II IDE flash programmer utility.

The Intel EPCS/EPCQA configuration device connects to the FPGA through dedicated pins on the FPGA, not through general-purpose I/O pins. In all Intel device families except Cyclone®  III, Cyclone® IV, and Intel® Cyclone® 10 LP the EPCS/EPCQA serial flash controller core does not create any I/O ports on the top-level Platform Designer system module. If the EPCS/EPCQA device and the FPGA are wired together on a board for configuration using the EPCS/EPCQA device (in other words, active serial configuration mode), no further connection is necessary between the EPCS/EPCQA serial flash controller core and the EPCS/EPCQA device. When you compile the Platform Designer system in the Intel® Quartus® Prime software, the EPCS/EPCQA serial flash controller core signals are routed automatically to the device pins for the EPCS/EPCQA device.

You, however, have the option not to use the dedicated pins on the FPGA (active serial configuration mode) by turning off the respective parameters in the MegaWizard interface. When this option is turned off or when the target device is a Cyclone® III, Cyclone® IV device, or Intel® Cyclone® 10 LP you have the flexibility to connect the output pins, which are exported to the top-level design, to any EPCS/EPCQA devices. Perform the following tasks in the Intel® Quartus® Prime software to make the necessary pin assignments:

  • On the Dual-purpose pins page (Assignments > Devices > Device and Pin Options), ensure that the following pins are assigned to the respective values:
    • Data[0] = Use as regular I/O
    • Data[1] = Use as regular I/O
    • DCLK = Use as regular I/O
    • FLASH_nCE/nCS0 = Use as regular I/O
  • Using the Pin Planner (Assignments > Pins), ensure that the following pins are assigned to the respective configuration functions on the device:
    • data0_to_the_epcs_controller = DATA0
    • sdo_from the_epcs_controller = DATA1,ASDO
    • dclk_from_epcs_controller = DCLK
    • sce_from_the_epcs_controller = FLASH_nCE