Embedded Peripherals IP User Guide

ID 683130
Date 8/15/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

55.5.3. Supported Features

This section describes the supported feature of Lightweight UART core. All these configurations are done in Platform Designer.

You may refer to Nios® II Software Developer Handbook and Nios® V Processor Quick Start Guide for details.

Note: All features supported by UART Core is supported by Lightweight UART Core.
Table 518.  Supported Features
Feature Parameter Description
Small driver
  • enable_small_driver
  • enable_reduced_device_drivers
Enables the small driver feature.
Note: Other features of the Lightweight UART core are not available when the small driver feature is enabled.
Hard Flow Control
  • Include CTS/RTS
The driver code sets the device flag with INTEL_LW_UART_FC.
EOP Service
  • Include end-of-packet
The driver code sets the device flag with INTEL_LW_UART_EOP.
Note: Use the driver api: intel_lw_uart_init_eop to set your custom function, which is called when the EOP interrupt is triggered.
TX and RX FIFO with configurable depth
  • Implement TXFIFO in register
    • Depth of TXFIFO – 8
  • Implement RXFIFO in register
    • Depth of RXFIFO - 8
The driver code allocates a static memory for the driver buffer based on the values shown below.
RX almost full
  • Remaining RXFIFO depth to assert almost full - 1
This feature is fully handled by the IP. If the flow control is enabled, the IP assert RTS upon this status.
Configurable baudrate
  • Fixed baud rate
  • At BSP Drivers:
    • enable_small_driver – must be disabled
    • enable_ioctl – to be checked
The fixed baud rate must be disabled, else IOCTL will not be processed.
Note: The baud rate is limited by the driver as clock frequency/4, as higher frequency will cause frame error and unexpected behavior.
RX and TX timeout
  • rx_timeout_cycle: -1
  • rx_timeout_us: 10
  • tx_timeout_cycle: -1
  • tx_timeout_us: 10
  • timeout_cycle is the number of cycles needed before a timeout is triggered.
  • timeout_us is the interval of each cycle in [us].
  • Timeout is used to avoid dead locks, but it will cause data loss.
  • Set timeout_cycle to -1 to disable this feature. The timeout feature is disabled by default.

As receiver, dead lock occurs when:

  • fread is called with the length parameter more than the received length.
  • The transmitter does not send the requested length.
  • Data corruption occurs (framing error, parity error, or break).

As transmitter, dead lock will occur when:

  • Flow control is enabled. The driver TX circular buffer is full. Somehow, the receiver does not empty the RX FIFO.
Note: When you are using the system function, estimate the correct length of TX and RX data to avoid deadlock. The driver waits for the data to arrive or sent in blocking mode. Use the timeout feature, but expect data lost to occur. Timeout is not available for small driver. You must also check for ALT_ERRNO and do error handling in your application.
Call back function for exception handling
  • intel_lw_uart_init_eh
You can use intel_lw_uart_init_eh to set your custom function for exception handling. This function is called when framing error, parity error, TXFIFO overrun error, RXFIFO overrun error, RXFIFO underrun error, or break is detected. The function has status and base address of device as input. The base address will identify the lw_uart instance. The status identifies which exception is triggered. Refer to intel_lw_uart_regs.h for the status mask. For framing and parity error, the driver automatically discards the corrupted data.
API to set and clear transmit break(TRBK)
  • intel_lw_uart_set_trbk
You can use intel_lw_uart_set_trbk in your application to set and clear TRBK control. When break is detected on RX side, the driver automatically discards the corrupted data.
Table 519.  Supported Software Features
Feature Parameter Description
Call back function for exception handling
  • intel_lw_uart_init_eh
You can use intel_lw_uart_init_eh to set your custom function for exception handling. This function is called when framing error, parity error, TXFIFO overrun error, RXFIFO overrun error, RXFIFO underrun error, or break is detected. The function has status and base address of device as input. The base address will identify the lw_uart instance. The status identifies which exception is triggered. Refer to intel_lw_uart_regs.h for the status mask. For framing and parity error, the driver automatically discards the corrupted data.
API to set and clear transmit break(TRBK)
  • intel_lw_uart_set_trbk
You can use intel_lw_uart_set_trbk in your application to set and clear TRBK control. When break is detected on RX side, the driver automatically discards the corrupted data.