Embedded Peripherals IP User Guide

ID 683130
Date 8/15/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

38.3. Register Maps

The VIC core CSRs are accessible through the Avalon® -MM interface. Software can configure the core and determine current status by accessing the registers.

Each register has a 32-bit interface that is not byte-enabled. You must access these registers with a host that is at least 32 bits wide.

Table 398.  Control Status Registers
Offset Register Name Access Reset Value Description
0 – 31 INT_CONFIG<n> R/W 0 There are 32 interrupt configuration registers (INT_CONFIG0INT_CONFIG31). Each register contains fields to configure the behavior of its corresponding interrupt. If an interrupt input does not exist, reading the corresponding register always returns zero, and writing is ignored. Refer to the INT_CONFIG Register Map table for the INT_CONFIG register map.
32 INT_ENABLE R/W 0 The interrupt enable register. INT_ENABLE holds the enabled status of each interrupt input. The 32 bits of the register map to the 32 interrupts available in the VIC core. For example, bit 5 corresponds to IRQ5. 45

Interrupts that are not enabled are never considered by the priority processing block, even when the interrupt input is asserted. This applies to both maskable and non-maskable interrupts.

33 INT_ENABLE_SET W 0 The interrupt enable set register. Writing a 1 to a bit in INT_ENABLE_SET sets the corresponding bit in INT_ENABLE. Writing a 0 to a bit has no effect. Reading from this register always returns 0. 45
34 INT_ENABLE_CLR W 0 The interrupt enable clear register. Writing a 1 to a bit in INT_ENABLE_CLR clears corresponding bit in INT_ENABLE. Writing a 0 to a bit has no effect. Reading from this register always returns 0. 45
35 INT_PENDING R 0 The interrupt pending register. INT_PENDING shows the pending interrupts. Each bit corresponds to one interrupt input.

If an interrupt does not exist, reading its corresponding INT_PENDING bit always returns 0, and writing is ignored.

Bits in INT_PENDING are set in the following ways:

An external interrupt is asserted at the VIC interface and the corresponding INT_ENABLE bit is set.

An SW_INTERRUPT bit is set and the corresponding INT_ENABLE bit is set.

INT_PENDING bits remain set as long as either condition applies. Refer to the Interrupt Request Block for details. 45

36 INT_RAW_STATUS R 0 The interrupt raw status register. INT_RAW_STATUS shows the unmasked state of the interrupt inputs.

If an interrupt does not exist, reading the corresponding INT_RAW_STATUS bit always returns 0, and writing is ignored.

A set bit indicates an interrupt is asserted at the interface of the VIC. The interrupt is asserted to the processor only when the corresponding bit in the interrupt enable register is set. 45

37 SW_INTERRUPT R/W 0 The software interrupt register. SW_INTERRUPT drives the software interrupts. Each interrupt is ORed with its external hardware interrupt and then enabled with INT_ENABLE. Refer to the Interrupt Request Block for details. 45
38 SW_INTERRUPT_SET W 0 The software interrupt set register. Writing a 1 to a bit in SW_INTERRUPT_SET sets the corresponding bit in SW_INTERRUPT. Writing a 0 to a bit has no effect. Reading from this register always returns 0. 45
39 SW_INTERRUPT_CLR W 0 The software interrupt clear register. Writing a 1 to a bit in SW_INTERRUPT_CLR clears the corresponding bit in SW_INTERRUPT. Writing a 0 to a bit has no effect. Reading from this register always returns 0. 
40 VIC_CONFIG R/W 0 The VIC configuration register. VIC_CONFIG allows software to configure settings that apply to the entire VIC. Refer to the VIC_CONFIG Register Map table for the VIC_CONFIG register map.
41 VIC_STATUS R 0 The VIC status register. VIC_STATUS shows the current status of the VIC. Refer to the VIC_STATUS Register Map table for the VIC_STATUS register map.
42 VEC_TBL_BASE R/W 0 The vector table base register. VEC_TBL_BASE holds the base address of the vector table in the processor’s memory space. Because the table must be aligned on a 4-byte boundary, bits 1:0 must always be 0.
43 VEC_TBL_ADDR R 0 The vector table address register. VEC_TBL_ADDR provides the RHA for the IRQ value with the highest priority pending interrupt. If no interrupt is active, the value in this register is 0.

If daisy chain input is enabled and is the highest priority interrupt, the vector table address register contains the RHA value from the daisy chain input interface.

Table 399.  The INT_CONFIG Register Map
Bits Field Name Access Reset Value Description
0:5 RIL R/W 0

The requested interrupt level field. RIL contains the interrupt level of the interrupt requesting service. The processor can use the value in this field to determine if the interrupt is of higher priority than what the processor is currently doing.

6 RNMI R/W 0 The requested non-maskable interrupt field. RNMI contains the non-maskable interrupt mode of the interrupt requesting service. When 0, the interrupt is maskable. When 1, the interrupt is non-maskable.
7:12 RRS R/W 0 The requested register set field. RRS contains the number of the processor register set that the processor should use for processing the interrupt. Software must ensure that only register values supported by the processor are used.
13:31 Reserved

For expanded definitions of the terms in the INT_CONFIG Register Map table, refer to the Exception Handling chapter of the Nios® II Software Developer’s Handbook.

Table 400.  The VIC_CONFIG Register Map
Bits Field Name Access Reset Value Description
0:2 VEC_SIZE R/W 0 The vector size field. VEC_SIZE specifies the number of bytes in each vector table entry. VEC_SIZE is encoded as log2 (number of words) - 2. Namely:

0—4 bytes per vector table entry

1—8 bytes per vector table entry

2—16 bytes per vector table entry

3—32 bytes per vector table entry

4—64 bytes per vector table entry

5—128 bytes per vector table entry

6—256 bytes per vector table entry

7—512 bytes per vector table entry

3 DC R/W 0 The daisy chain field. DC serves the following purposes:

Enables and disables the daisy chain input interface, if present. Write a 1 to enable the daisy chain interface; write a 0 to disable it.

Detects the presence of the daisy chain input interface. To detect, write a 1 to DC and then read DC. A return value of 1 means the daisy chain interface is present; 0 means the daisy chain interface is not present.

4:31 Reserved
Table 401.  The VIC_STATUS Register Map
Bits Field Name Access Reset Value Description
0:5 HI_PRI_IRQ R 0 The highest priority interrupt field. HI_PRI_IRQ contains the IRQ number of the active interrupt with the highest RIL. When there is no active interrupt (IP is 0), reading from this field returns 0.

When the daisy chain input is enabled and it is the highest priority interrupt, then the value read from this field is 32.

Bit 5 always reads back 0 when the daisy chain input is not present.

6:30 Reserved
31 IP R 0 The interrupt pending field. IP indicates when there is an interrupt ready to be serviced. A 1 indicates an interrupt is pending; a 0 indicates no interrupt is pending.
45 This register contains a 1-bit field for each of the 32 interrupt inputs. When the VIC is configured for less than 32 interrupts, the corresponding 1-bit field for each unused interrupts is tied to zero. Reading these locations always returns 0, and writing is ignored. To determine which interrupts are present, write the value 0xffffffff to the register and then read the register contents. Any bits that return zero do not have an interrupt present.