AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

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ID 683262
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Platform Design Strategy for 56G PAM4 Channels 3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2. Platform Design Strategy for 56G PAM4 Channels x
2.1. Intel® Stratix® 10 E-Tile Transceiver Channel Usage Mode 2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2) 2.3. PCB Design Flow
2.3. PCB Design Flow x
2.3.1. Design Target at 56 Gbps PAM4 Standard 2.3.2. PCB Materials and Stackup Design 2.3.3. FPGA PCB Design 2.3.4. PCB Pre-Layout Simulation Phase 2.3.5. PCB Post-Layout Simulation Phase
2.3.2. PCB Materials and Stackup Design x
2.3.2.1. Insertion Loss 2.3.2.2. Return Loss 2.3.2.3. Package Loss and Crosstalk 2.3.2.4. PCB Via Design 2.3.2.5. PCB Connector 2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design x
2.3.3.1. FPGA PCB Breakout Design and Reference 2.3.3.2. P/N De-skew Strategy on Differential Pairs 2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

2.3.2.3. Package Loss and Crosstalk

The package loss for the Intel® Stratix® 10 E-Tile is summarized below for designers' end-to-end channel loss estimation/evaluation:
  • Impedance specification: 90 ohm +/- 10%
  • Maximum differential insertion loss: -3 dB (Tx or Rx) at the Nyquist frequency
  • Differential return loss: better than -15 dB up to the Nyquist frequency
  • Crosstalk (up to the Nyquist frequency)
    • NEXT < -60 dB
    • FEXT < -50 dB
Level Two Title