AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

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ID 683262
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Platform Design Strategy for 56G PAM4 Channels 3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2. Platform Design Strategy for 56G PAM4 Channels x
2.1. Intel® Stratix® 10 E-Tile Transceiver Channel Usage Mode 2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2) 2.3. PCB Design Flow
2.3. PCB Design Flow x
2.3.1. Design Target at 56 Gbps PAM4 Standard 2.3.2. PCB Materials and Stackup Design 2.3.3. FPGA PCB Design 2.3.4. PCB Pre-Layout Simulation Phase 2.3.5. PCB Post-Layout Simulation Phase
2.3.2. PCB Materials and Stackup Design x
2.3.2.1. Insertion Loss 2.3.2.2. Return Loss 2.3.2.3. Package Loss and Crosstalk 2.3.2.4. PCB Via Design 2.3.2.5. PCB Connector 2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design x
2.3.3.1. FPGA PCB Breakout Design and Reference 2.3.3.2. P/N De-skew Strategy on Differential Pairs 2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

2.3.5. PCB Post-Layout Simulation Phase

Post-layout simulation is a mandatory design phase for the Intel® Stratix® 10 E-Tile high-speed data links. Follow the steps below in your post-layout simulation:
  • Pick three or more pairs of channels with the worst via coupling for s-parameter extraction for the impedance and crosstalk validation.
  • Perform time-domain channel eye simulation with the IBIS-AMI models while the actual channel model is being extracted.

Strategy for Post-Layout PCB Channel Modeling

  • Extract the entire PCB channel in the E/M solver (not recommended)
    • The extraction takes a long time to finish and is not even possible for many complicated cases.
    • Connector pads do not have proper coupling to the connector, and may be double-counted when cascading with the connector model.
  • Use the divide-and-conquer method (recommended)
    • Cut the channel at the trace near the FPGA/connector pad/via boundary.
    • Solve the trace-only portion.
    • Solve the FPGA via with the package ball and ground reference.
    • Solve the connector pad/via with the connector together. This step may require SI support from the connector vendor.
    • Cascade all pieces solved individually to build the whole channel eye simulation with the IBIS-AMI model.
The following figure shows a channel model extraction example using the recommended procedure, i.e. the divide-and-conquer methodology.
Figure 25. Divide and Conquer Methodology in Channel Model Extraction
This figure shows a group of four RX channels selected from the actual layout of a PCB. The benefits of the divide-and-conquer methodology to this example are:
  • No double counting of the QSFP pin pads when combining with the QSFP connector model.
  • The different portions of the channel can be simulated faster individually, and these simulations can be run in parallel.
  • A 2.5D E/M solver may be good enough for trace-only geometries.
  • Trace setup is easier and includes the etching effect.

The only disadvantage of the divide-and-conquer method is that it takes a longer time to prepare the cutouts and settings. However, the time cost can be improved with clearly specified steps.

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