Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.7.1. Transceiver Dedicated Clocks

Dedicated clocking scheme that is implemented on the Intel® Stratix® 10 TX transceiver signal integrity development board allows different protocols to run simultaneously by the Intel® Stratix® 10 TX FPGA.

Differential clock sources are provided from an I2C programmable oscillator or PLL to the dedicated REFCLK input pins of transceiver blocks on both sides of the FPGA. The default frequencies for the oscillator and PLL at startup are:
  • 156.25 MHz (Y1 and U3)
  • 322.265625 MHz (U3)
  • 176.5625 MHz (U3)
  • 307.2 MHz (U3)
The default frequencies can be overridden and a different frequency can be programmed into the oscillators and PLLs for support of other protocols.
Note: Programmed frequencies are lost upon a board power down. Oscillator and PLL frequencies return to their default frequency upon power up.

The oscillator or PLL provides a differential LVDS trigger output to SMA connectors for scope or other laboratory equipment triggering purposes.

In addition to the two oscillators and PLLs, each transceiver tile have dedicated differential REFCLK input from a pair of SMA connectors to allow use of laboratory equipment clock generators as the transceiver clock source.

The six inputs below connect directly to the transceiver clock inputs:
  • J34/J35 SMA connector direct connection to H-tile block
  • J36/J37 SMA connector direct connection to E-tile 8B block
  • J38/J39 SMA connector direct connection to E-tile 8C block
  • J40/J41 SMA connector direct connection to E-tile 9A block
  • J42/J43 SMA connector direct connection to E-tile 9B block
  • J44/J45 SMA connector direct connection to E-tile 9C block

The figure below shows the dedicated transceiver clocks that are implemented on the Intel® Stratix® 10 TX FPGA development kit.

Figure 7. Transceiver Clocks
Level Two Title