AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

Download PDF
ID 683783
Date 7/26/2019
Public
Document Table of Contents
Document Table of Contents x
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. AN 839: Design Block Reuse Tutorial Document Revision History
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
Process Description Completed Tutorial Files Tutorial Module Steps Command-Line Alternative Step 1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. Step 4: Hardware Verification (Optional)
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

1.5. Core Partition Reuse—Consumer Tutorial

Follow the steps in this tutorial module to reuse a core partition in a Consumer project.

Process Description

As a core partition Consumer, you receive the final core partition that the Developer provides. The Consumer adds the black box file and assigns the .qdb in the Consumer project. Because the exported .qdb includes compiled netlist information, the Consumer project must target the same FPGA device part number, and use the same Intel® Quartus® Prime version as the Developer project.

Figure 11. File Exchange Between Developer and Consumer

The Consumer must specify all signals and port directions, as well as any Verilog HDL parameters or VHDL generics. The Developer can optionally include an .sdc for the partition to verify the partition timing results after full integration in the Consumer project.

Completed Tutorial Files

The Core_Partition_Reuse/Completed/Consumer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

Command-Line Alternative Step

You can skip Step 1: Add Files and Run Synthesis through Step 3: Compile the Design in this tutorial module by adding following lines to the .qsf, and then running the Core_Partition_Reuse/Consumer/Script/run.sh script: 

#Create the partition
set_instance_assignment -name PARTITION blinking_led \
     -to u_blinking_led -entity top
#Assign the .qdb file to the partition
set_instance_assignment -name QDB_FILE_PARTITION blinking_led.qdb \
     -to u_blinking_led -entity top
#Add the BB file to the file list
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_bb.sv
Level Two Title