AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683783
Date 7/26/2019
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Document Table of Contents
Document Table of Contents x
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. AN 839: Design Block Reuse Tutorial Document Revision History
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. Step 4: Hardware Verification (Optional)
1.6. Root Partition Reuse—Developer Tutorial x
Process Description Completed Tutorial Files Tutorial Module Steps Command-Line Alternative Tutorial Step 1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

1.6. Root Partition Reuse—Developer Tutorial

Follow the steps in this tutorial module to develop a root partition for reuse.

Process Description

As a root partition Developer, you create, compile, and eventually export a top-level root partition that includes the device periphery. The Developer also reserves a core partition for subsequent development of core logic in the Consumer project.

Figure 15. Root Partition Reuse Flow

The Developer fully compiles this design and then provides the root partition .qdb and an .sdc file for the top-level design.

The following figure shows the Developer's root partition with a placeholder for the blinking_led module. For this tutorial, blinking_led simply ties the outputs to 4’b1111 to turn off the LEDs.

Figure 16.  RTL View of Developer's Root Partition

Completed Tutorial Files

The Root_Partition_Reuse/Completed/Developer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

Command-Line Alternative Tutorial Step

You can skip Step 1: Create a Reserved Core Partition through Step 3: Compile and Export the Root Partition in this tutorial module by adding the following lines to the .qsf, and then running the Root_Partition_Reuse/Developer/Script/run.sh script. 

set_instance_assignment -name PARTITION blinking_led \
     -to u_blinking_led -entity top
set_instance_assignment -name PERIPHERY_REUSE_CORE ON -to \
     u_blinking_led -entity top
set_instance_assignment -name PLACE_REGION \
     "X63 Y102 X185 Y162" -to u_blinking_led
set_instance_assignment -name RESERVE_PLACE_REGION ON -to \
     u_blinking_led
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON \
     -to u_blinking_led
set_instance_assignment -name REGION_NAME u_blinking_led -to \
     u_blinking_led
set_instance_assignment -name ROUTE_REGION \
     "X63 Y102 X185 Y162" -to u_blinking_led
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \
     root_partition.qdb -to | -entity top
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