AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683783
Date 7/26/2019
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Document Table of Contents x
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. AN 839: Design Block Reuse Tutorial Document Revision History
1.4. Core Partition Reuse—Developer Tutorial x
Process Description Completed Tutorial Files Tutorial Steps Command-Line Alternative Step 1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. Step 4: Hardware Verification (Optional)
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

1.4. Core Partition Reuse—Developer Tutorial

Follow the steps in this tutorial module to develop a core partition for export and reuse in a Consumer project.

Process Description

As an IP Developer, you define, place, route, and eventually export a block of code within a partition. You then pass the exported .qdb to a Consumer.

Figure 3. Core Partition Reuse Flow

Reuse of the core partition also requires that you provide a black box file to the Consumer. The black box file defines the ports and port interface types for synthesis in the Consumer project. The Compiler ignores any further RTL that you include in the black box file.

You add the black box file to the Consumer project as a source file. You assign the exported .qdb file to a partition in the Consumer design. The .qdb file contains all of the information from the Developer's compilation snapshot. The Consumer can then reuse these compilation results in their project. The synthesis snapshot includes only synthesis results. The final snapshot includes synthesis, placement, and routing results.

Completed Tutorial Files

The Core_Partition_Reuse/Completed/Developer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Steps

This tutorial module includes the following steps:

Command-Line Alternative Step

You can skip Step 1: Define a Core Partition and Step 2: Compile and Export the Core Partition in this tutorial module by adding the following line to the Intel® Quartus® Prime Settings file (.qsf), and then running the Core_Partition_Reuse/Developer/Script/run.sh script. 

set_instance_assignment -name PARTITION blinking_led -to \
     u_blinking_led -entity top
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