Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

10.5.1.1.1. Implementation Details

The following table shows the parameter settings for the cache controller.

Table 67.  Cache Controller Configuration

Feature

Meaning

Cache way size

64 KB

Number of cache ways

8 ways

Tag RAM write latency

1

Tag RAM read latency

1

Tag RAM setup latency

1

Data RAM write latency

1

Data RAM read latency

2

Data RAM setup latency

1

Parity logic

Parity logic enabled

Lockdown by master

Lockdown by master enabled

Lockdown by line

Lockdown by line enabled

AXI ID width on slave ports

6 AXI ID bits on slave ports

Address filtering

Address filtering logic enabled

Speculative read

Logic for supporting speculative read enabled

Presence of ARUSERMx and AWUSERMx sideband signals

Sideband signals enabled