Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

29.2.2. User Clocks

A user clock is a PLL output that is connected to the FPGA fabric rather than the HPS. You can connect a user clock to logic that you instantiate in the FPGA fabric.

  • h2f_user0_clock—HPS-to-FPGA user clock, driven from main PLL
  • h2f_user1_clock—HPS-to-FPGA user clock, driven from peripheral PLL
  • h2f_user2_clock—HPS-to-FPGA user clock, driven from SDRAM PLL
Note: At power-up or reset, when CSEL[3:0]=0x0 or BSEL[2:0] is configured to boot from FPGA, the HPS PLLs are in bypass mode. Thus, HPS user clocks exported to the FPGA fabric run at osc1_clk frequency. For more information refer to the Clock Selection section.