Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

18.6.1. System Level EMAC Configuration Registers

In addition to the registers in the Ethernet Controller, there are other system level registers in the Clock Manager, System Manager and Reset Manager that must be programmed in order to configure the EMAC and its interfaces.

The following table gives a summary of the important System Manager clock register bits that control operation of the EMAC. These register bits are static signals that must be set while the corresponding EMAC is in reset.

Table 189.  System Manager Clock and Interface Settings
Register.Field Description

ctrl.ptpclksel_0

ctrl.ptpclksel_1

1588 PTP reference clock. This bit selects the source of the 1588 PTP reference clock.
  • 0x0= osc1_clk (default from Clock Manager)
  • 0x1= fpga_ptp_ref_clk (from FPGA fabric; in this case, the FPGA must be in usermode with an active reference clock)

ctrl.physel_0

ctrl.physel_1

PHY Interface Select. These two bits set the PHY mode.
  • 0x0= GMII or MII
  • 0x1= RGMII
  • ox2= RMII (default)
Note: Selecting the 0x0 encoding routes the GMII/MII signals to the FPGA fabric only and selecting the 0x1 encoding routes the RGMII signals to the HPS only. 0x2 is not a valid encoding and depending on the interface selected, must be changed to 0x0 or 0x1 out of reset.

The following table summarizes the important System Manager configuration register bits. All of the fields, except the AXI cache settings, are assumed to be static and must be set before the EMAC is brought out of reset. If the FPGA interface is used, the FPGA must be in user mode and enabled with the appropriate clock signals active before the EMAC can be brought out of reset.

Table 190.  System Manager Static Control Settings
Register.Field Description

module.emac_0

module.emac_1

FPGA interface to EMAC disable. This field is used to disable signals from the FPGA to the EMAC modules that could potentially interfere with their normal operation
  • 0x0= Disable (default)
  • 0x1=Enable

l3master.awcache_1

l3master.awcache_0

l3master.arcache_1

l3master.arcache_0

EMAC AXI Master AxCACHE settings. It is recommended that these bits are set while the EMAC is idle or in reset.

Various registers within the Clock Manager must also be configured in order for the EMAC controller to perform properly.

Table 191.  Clock Manager Settings
Register.Field Description

emac0clk.cnt

emac1clk.cnt

EMAC clock control. The cnt value in this register is used to divide the PLL VCO frequency to generate emac0clk and emac1clk.

en.emac0clk

en.emac1clk

emac0clk and emac1clk output enable.