Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

A.4.4.3.2. Quad SPI Flash Delay Configuration

The delay register in the quad SPI controller configures relative delay of the generation of the master output signals. All timings are defined in cycles of qspi_ref_clk.

The quad SPI flash memory must meet the following timing requirements:

  • TSLCH: 20 ns
    • TSLCH is used to calculate the init field (delay[7:0]) in the delay register. The init field represents the delay in qspi_ref_clk clocks between pulling the device chip select (qspi_n_ss_out) low and the first bit transfer.
  • TCHSH: 20 ns
    • TCHSH is used to calculate the after field (delay[15:8]) in the delay register. The after field represents the delay in the qspi_ref_clk clocks between last bit of the current transaction and the deassertion of the device chip select (qspi_n_ss_out).
  • TSHSL: 200 ns
    • TSHSL is used to calculate the nss field (delay[31:24]) in the delay register and is the delay in the qspi_ref_clk clocks for the length that the master mode chip select outputs are deasserted between transactions.
  • Tqspi_ref_clk is the master reference clock/external clock, qspi_ref_clk.

The formulas to calculate the fields in the delay register are:

delay[7:0]= init = TSLCH/Tqspi_ref_clk

delay[15:8]= after = TCHSH/Tqspi_ref_clk

delay[31:24]= nss = (TSHSL - Tqspi_clk)/Tqspi_ref_clk

Table 278.  Quad SPI Flash Delay Configuration
CSEL[1:0] Pin Value

Tqspi_ref_clk

(ns)

Tqspi_clk

(ns)

Device Delay Register
delay[7:0] (init) delay[15:8] (after) delay[31:24] (nss)
0 20 80 1 1 6
1 10 40 2 2 16
2–3 5 20 4 4 36

Read data capture delay is also configured when booting from QSPI. Depending on the CSEL pin settings, the Boot ROM configures the delay field of the rddatacap register in the QSPI differently. When CSEL Pins[1:0]=0x0 or 0x1, the Boot ROM leaves the delay field in the rddatacap register untouched. When CSEL Pins[1:0]= 0x2 or 0x3, the boot ROM calibrates the interface by reading the QSPI signal for all delay values of the rddatacap register. The Boot ROM analyzes all of the delay values that return a valid signature and uses the delay value in the middle of the valid window as the value it programs into the delay field of the rddatacap register.