Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

16.5.3. Indirect Read Operation with DMA Enabled

The following steps describe the general software flow to set up the quad SPI controller for indirect read operation with the DMA enabled:

  1. Perform the steps described in the Setting Up the Quad SPI Flash Controller section.
  2. Set the flash memory start address in the indrdstaddr register.
  3. Set the number of bytes to be transferred in the indrdcnt register.
  4. Set the indirect transfer trigger address in the indaddrtrig register.
  5. Set the number of bytes for single and burst type DMA transfers in the dmaper register.
  6. Optionally set the SRAM watermark level in the indrdwater register to control the rate DMA requests are issued.
  7. Start an indirect read access by setting the start field of the indrd register to 1.
  8. Either use the indirect complete interrupt to determine when the indirect read operation has completed or poll the completion status of the indirect read operation through the ind_ops_done_status field of the indrd register.