Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 12/04/2023
Public

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4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts

Follow these steps to incorporate the generated ActiveHDL* or Riviera Pro* simulation scripts into a top-level project simulation script.
  1. The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, sim_top.tcl.
    # # TOP-LEVEL TEMPLATE - BEGIN
    # #
    # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
    # # construct paths to the files required to simulate the IP in your Quartus
    # # project. By default, the IP script assumes that you are launching the
    # # simulator from the IP script location. If launching from another
    # # location, set QSYS_SIMDIR to the output directory you specified when you
    # # generated the IP script, relative to the directory from which you launch
    # # the simulator.
    # #
    # set QSYS_SIMDIR <script generation output directory>
    # #
    # # Source the generated IP simulation script.
    # source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
    # #
    # # Set any compilation options you require (this is unusual).
    # set USER_DEFINED_COMPILE_OPTIONS <compilation options>
    # set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
    # set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
    # #
    # # Call command to compile the Quartus EDA simulation library.
    # dev_com
    # #
    # # Call command to compile the Quartus-generated IP simulation files.
    # com
    # #
    # # Add commands to compile all design files and testbench files, including
    # # the top level. (These are all the files required for simulation other
    # # than the files compiled by the Quartus-generated IP simulation script)
    # #
    # vlog -sv2k5 <your compilation options> <design and testbench files>
    # #
    # # Set the top-level simulation or testbench module/entity name, which is
    # # used by the elab command to elaborate the top level.
    # #
    # set TOP_LEVEL_NAME <simulation top>
    # #
    # # Set any elaboration options you require.
    # set USER_DEFINED_ELAB_OPTIONS <elaboration options>
    # #
    # # Call command to elaborate your design and testbench.
    # elab
    # #
    # # Run the simulation.
    # run
    # #
    # # Report success to the shell.
    # exit -code 0
    # #
    # # TOP-LEVEL TEMPLATE - END
    
  2. Delete the first two characters of each line (comment and space):
     # TOP-LEVEL TEMPLATE - BEGIN
     #
     # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
     # construct paths to the files required to simulate the IP in your Quartus
     # project. By default, the IP script assumes that you are launching the
     # simulator from the IP script location. If launching from another
     # location, set QSYS_SIMDIR to the output directory you specified when you
     # generated the IP script, relative to the directory from which you launch
     # the simulator.
     #
     set QSYS_SIMDIR <script generation output directory>
     #
     # Source the generated IP simulation script.
     source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
     #
     # Set any compilation options you require (this is unusual).
     set USER_DEFINED_COMPILE_OPTIONS <compilation options>
     set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
     set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
     #
     # Call command to compile the Quartus EDA simulation library.
     dev_com
     #
     # Call command to compile the Quartus-generated IP simulation files.
     com
     #
     # Add commands to compile all design files and testbench files, including
     # the top level. (These are all the files required for simulation other
     # than the files compiled by the Quartus-generated IP simulation script)
     #
     vlog -sv2k5 <your compilation options> <design and testbench files>
     #
     # Set the top-level simulation or testbench module/entity name, which is
     # used by the elab command to elaborate the top level.
     #
     set TOP_LEVEL_NAME <simulation top>
     #
     # Set any elaboration options you require.
     set USER_DEFINED_ELAB_OPTIONS <elaboration options>
     #
     # Call command to elaborate your design and testbench.
     elab
     #
     # Run the simulation.
     run
     #
     # Report success to the shell.
     exit -code 0
     #
     # TOP-LEVEL TEMPLATE - END
    
  3. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  4. Refer to the following sim_top.tcl example content, where this file is in the same aldec/ sub-folder as the rivierapro_setup.tcl file.
    # TOP-LEVEL TEMPLATE - BEGIN
    #
    # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
    # construct paths to the files required to simulate the IP in your Quartus
    # project. By default, the IP script assumes that you are launching the
    # simulator from the IP script location. If launching from another
    # location, set QSYS_SIMDIR to the output directory you specified when you
    # generated the IP script, relative to the directory from which you launch
    # the simulator.
    #
    set QSYS_SIMDIR ../
    #
    # Source the generated IP simulation script.
     source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
     #
     # Set any compilation options you require (this is unusual).
    set USER_DEFINED_COMPILE_OPTIONS "" 
    set USER_DEFINED_VHDL_COMPILE_OPTIONS "" 
    set USER_DEFINED_VERILOG_COMPILE_OPTIONS "" 
    #
     # Call command to compile the Quartus EDA simulation library.
    dev_com
     #
     # Call command to compile the Quartus-generated IP simulation files.
    com
     #
     # Add commands to compile all design files and testbench files, including
     # the top level. (These are all the files required for simulation other
     # than the files compiled by the Quartus-generated IP simulation script)
     #
    vlog -sv2k5 $QSYS_SIMDIR/PLL_RAM.v
    vlog -sv2k5 $QSYS_SIMDIR/testbench_1.v
     #
     # Set the top-level simulation or testbench module/entity name, which is
     # used by the elab command to elaborate the top level.
     #
    set TOP_LEVEL_NAME tb
     #
     # Set any elaboration options you require.
     set USER_DEFINED_ELAB_OPTIONS "" 
     #
     # Call command to elaborate your design and testbench.
     elab
     #
     # Run the simulation.
    run -all
     #
     # Report success to the shell.
     exit -code 0
     #
     # TOP-LEVEL TEMPLATE - END
    
  5. To view all available options, invoke the Active-HDL or Riviera-PRO license and launch the simulator by typing vsim in command-line mode. After the simulator launches, type help in the simulator Console panel. To view options related to a specific command, for example the vsim simulation command, type help vsim in the simulator Console panel.
  6. Run the new top-level script from the generated simulation directory in command-line mode. To run the simulation in GUI mode, type the following:
    vsim -gui -l log.txt +access +r -lib dsn tb -do sim_top.tcl

    To run the simulation in command-line mode, type the following:

    vsim –c –do sim_top.tcl