Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts

  1. The generated xcelium/xmsim_setup.sh simulation script contains the following template lines. Cut and paste these lines into a new top-level script, for example xmsim.sh. This new top-level script calls the generated simulation script, xmsim_setup.sh.
    # # TOP-LEVEL TEMPLATE - BEGIN
    # #
    # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
    # # construct paths to the files required to simulate the IP in your Quartus
    # # project. By default, the IP script assumes that you are launching the
    # # simulator from the IP script location. If launching from another
    # # location, set QSYS_SIMDIR to the output directory you specified when you
    # # generated the IP script, relative to the directory from which you launch
    # # the simulator. In this case, you must also copy the generated files
    # # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
    # # into the location from which you launch the simulator, or incorporate
    # # into any existing library setup.
    # #
    # # Run Quartus-generated IP simulation script once to compile Quartus EDA
    # # simulation libraries and Quartus-generated IP simulation files, and copy
    # # any ROM/RAM initialization files to the simulation directory.
    # # - If necessary, specify any compilation options:
    # #   USER_DEFINED_COMPILE_OPTIONS
    # #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
    # #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
    # #
    # source <script generation output directory>/xcelium/xcelium_setup.sh \
    # SKIP_ELAB=1 \
    # SKIP_SIM=1 \
    # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
    # USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
    # USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
    # QSYS_SIMDIR=<script generation output directory>
    # #
    # # Compile all design files and testbench files, including the top level.
    # # (These are all the files required for simulation other than the files
    # # compiled by the IP script)
    # #
    # xmvlog <compilation options> <design and testbench files>
    # #
    # # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
    # # testbench module/entity name.
    # #
    # # Run the IP script again to elaborate and simulate the top level:
    # # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
    # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
    # #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
    # #
    # source <script generation output directory>/xcelium/xcelium_setup.sh \
    # SKIP_FILE_COPY=1 \
    # SKIP_DEV_COM=1 \
    # SKIP_COM=1 \
    # TOP_LEVEL_NAME=<simulation top> \
    # USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
    # USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
    # #
    # # TOP-LEVEL TEMPLATE - END
    
  2. Delete the first two characters of each line (comment and space):
     # TOP-LEVEL TEMPLATE - BEGIN
     #
     # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
     # construct paths to the files required to simulate the IP in your Quartus
     # project. By default, the IP script assumes that you are launching the
     # simulator from the IP script location. If launching from another
     # location, set QSYS_SIMDIR to the output directory you specified when you
     # generated the IP script, relative to the directory from which you launch
     # the simulator. In this case, you must also copy the generated files
     # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
     # into the location from which you launch the simulator, or incorporate
     # into any existing library setup.
     #
     # Run Quartus-generated IP simulation script once to compile Quartus EDA
     # simulation libraries and Quartus-generated IP simulation files, and copy
     # any ROM/RAM initialization files to the simulation directory.
     # - If necessary, specify any compilation options:
     #   USER_DEFINED_COMPILE_OPTIONS
     #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
     #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
     #
     source <script generation output directory>/xcelium/xcelium_setup.sh \
     SKIP_ELAB=1 \
     SKIP_SIM=1 \
     USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
     USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
     USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
     QSYS_SIMDIR=<script generation output directory>
     #
     # Compile all design files and testbench files, including the top level.
     # (These are all the files required for simulation other than the files
     # compiled by the IP script)
     #
     xmvlog <compilation options> <design and testbench files>
     #
     # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
     # testbench module/entity name.
     #
     # Run the IP script again to elaborate and simulate the top level:
     # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
     # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
     #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
     #
     source <script generation output directory>/xcelium/xcelium_setup.sh \
     SKIP_FILE_COPY=1 \
     SKIP_DEV_COM=1 \
     SKIP_COM=1 \
     TOP_LEVEL_NAME=<simulation top> \
     USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
     USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
     #
     # TOP-LEVEL TEMPLATE - END
    
  3. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  4. Refer to the following xmsim.sh example content, where this file is in the same /xcelium sub-folder as the xmsim_setup.sh file.
    # TOP-LEVEL TEMPLATE - BEGIN
    #
    # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
    # construct paths to the files required to simulate the IP in your Quartus
    # project. By default, the IP script assumes that you are launching the
    # simulator from the IP script location. If launching from another
    # location, set QSYS_SIMDIR to the output directory you specified when you
    # generated the IP script, relative to the directory from which you launch
    # the simulator. In this case, you must also copy the generated files
    # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
    # into the location from which you launch the simulator, or incorporate
    # into any existing library setup.
    #
    # Run Quartus-generated IP simulation script once to compile Quartus EDA
    # simulation libraries and Quartus-generated IP simulation files, and copy
    # any ROM/RAM initialization files to the simulation directory.
    # - If necessary, specify any compilation options:
    #   USER_DEFINED_COMPILE_OPTIONS
    #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
    #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
    #
    source ./xcelium_setup.sh \
    SKIP_ELAB=1 \
    SKIP_SIM=1 \
    USER_DEFINED_COMPILE_OPTIONS="" \
    USER_DEFINED_VHDL_COMPILE_OPTIONS="" \
    USER_DEFINED_VERILOG_COMPILE_OPTIONS="" \
    QSYS_SIMDIR=./../
    #
    # Compile all design files and testbench files, including the top level.
    # (These are all the files required for simulation other than the files
    # compiled by the IP script)
    #
    xmvlog $QSYS_SIMDIR/PLL_RAM.v
    xmvlog $QSYS_SIMDIR/UP_COUNTER_IP/UP_COUNTER_IP.v
    xmvlog $QSYS_SIMDIR/DOWN_COUNTER_IP/DOWN_COUNTER_IP.v
    xmvlog $QSYS_SIMDIR/ClockPLL/ClockPLL.v
    xmvlog $QSYS_SIMDIR/RAMhub/RAMhub.v
    xmvlog $QSYS_SIMDIR/testbench_1.v
    #
    # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
    # testbench module/entity name.
    #
    # Run the IP script again to elaborate and simulate the top level:
    # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
    # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
    #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
    #
     source ./xcelium_setup.sh \
    SKIP_FILE_COPY=1 \
    SKIP_DEV_COM=1 \
    SKIP_COM=1 \
    TOP_LEVEL_NAME="tb" \
    USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps\ -NOWARN\ CSINFI" \
    USER_DEFINED_SIM_OPTIONS="-GUI"
    #
    # TOP-LEVEL TEMPLATE - END
    
  5. Run the resulting top-level script by typing the following at the command-line:
    sh xmsim.sh

    Specify the path to this file if you run it from a different directory.