MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.5.1.6. Consider the guidelines to plan for debugging tools

  • Select on-chip debugging schemes early to plan memory and logic requirements, I/O pin connections, and board connections.
  • If you want to use Signal Probe incremental routing, the Signal Tap II Embedded Logic Analyzer, Logic Analyzer Interface, In-System Memory Content Editor, In-System Sources and Probes, or Virtual JTAG IP core, plan your system and board with JTAG connections that are available for debugging.
  • Plan for the small amount of additional logic resources used to implement the JTAG hub logic for JTAG debugging features.
  • For debugging with the Signal Tap II Embedded Logic Analyzer, reserve device memory resources to capture data during system operation.
  • Reserve I/O pins for debugging with Signal Probe or the Logic Analyzer Interface so that you do not have to change the design or board to accommodate debugging signals later.
  • Ensure the board supports a debugging mode where debugging signals do not affect system operation.
  • Incorporate a pin header or micro connector as required for an external logic analyzer or mixed signal oscilloscope.
  • To use debug tools incrementally and reduce compilation time, ensure incremental compilation is on so you do not have to recompile the design to modify the debug tool.
  • To use the Virtual JTAG IP core for custom debugging applications, instantiate it in the HDL code as part of the design process.
  • To use the In-System Sources and Probes feature, instantiate the IP core in the HDL code.
  • To use the In-System Memory Content Editor for RAM or ROM blocks or the LPM_CONSTANT IP core, turn on the Allow In-System Memory Content Editor option to capture and update content independently of the system clock option for the memory block in the parameter editor.