MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.7.6. Enable the chip-wide reset to clear all registers if required

MAX® 10 devices support an optional chip-wide reset that enables you to override all clears on all device registers, including the registers of the memory blocks (but not the memory contents).
  • DEV_CLRn pin is driven low—all registers are cleared or reset to 0. The affected register behave as if they are preset to a high value when synthesis performs an optimization called NOT-gate-push back due to register control signals.
  • DEV_CLRn pin is driven high—all registers behave as programmed.

    To enable chip-wide reset, before compiling your design, turn on Enable device-wide reset (DEV_CLRn) under the Options list of the General category in the Device and Pin Options dialog box of the Quartus Prime software.