MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.5.3.4. Verify the JTAG pin connections to the download cable header

A device operating in JTAG mode uses the required TDI, TDO, TMS, and TCK pins. The TCK pin does not support internal weak pull-down.
There are two JTAG pin connections settings to the download cable header that you can set up:
  1. If the connection between the JTAG pin connections and download cable header is set up without the use of diodes and capacitors, connect the TCK pin to an external 1-kΩ to 10-kΩ pull-down resistor. The TDI and TMS pins have weak internal pull-up resistors. The JTAG output pin (TDO) and all JTAG input pins are powered by VCCIO. The voltage range is 1.5 V to 3.3 V. The download cable must be powered at 2.5 V when VCCIO of the JTAG pins is powered at 2.5 V to 3.3 V to prevent voltage overshoot because the JTAG pins do not have internal PCI* clamping diodes. The TCK pin must be pulled to ground. If the VCCIO of the JTAG pins is powered at 1.5 V or 1.8 V, the download cable should be powered by the same VCCIO.
  2. For the setting of JTAG pin connections to the download cable header with diodes and capacitors being used, the download cable must be powered up with VCCIO Bank 1 for 10M02 devices or VCCIO Bank 1B for all other MAX® 10 devices. The need for regulating the voltage in Setting (1) is not required because the use of diodes and capacitors can prevent voltage overshoot. Refer to the JTAG Configuration Setup in the MAX® 10 FPGA Configuration User Guide for the details of this setting.