MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.8.2.2. Review the Timing Analyzer reports after compilation

The Quartus® Prime software includes the Quartus® Prime Timing Analyzer, a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design. It supports the industry standard Synopsys* Design Constraints (SDC) format timing constraints, and has an easy-to-use GUI with interactive timing reports. It is ideal for constraining high-speed source-synchronous interfaces and clock multiplexing design structures.

The software also supports static timing analysis in the industry-standard Synopsys* Primetime software. To generate the required timing netlist, specify the tool in the New Project Wizard or the EDA Tools Settings page of the Settings dialog box.