MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.7.3. Use IP cores with the parameter editor

Instead of coding your own logic, save your design time by using Altera FPGA IP cores—a library of parameterized modules and device-specific IP cores. The IP cores are optimized for Altera FPGA device architectures and can offer more efficient logic synthesis and device implementation.

To ensure that you set all ports and parameters correctly, use the Quartus® Prime parameter editor to build or change IP cores parameters.

For detailed information about a specific IP core, refer to the respective MAX® 10 user guides.