Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

4.2.1.1. Cold Reset Assertion Sequence

The following list describes the assertion steps for cold reset shown in the Cold Reset timing diagram:

  1. Assert module resets
  2. Wait for 32 cycles. Deassert clock manager cold reset.
  3. Wait for 96 cycles (so clocks can stabilize).
  4. Proceed to the “Cold and Warm Reset Deassertion Sequence” section using the following link.