Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

11.5.3.1. csCTI

This section lists the trigger input, output, and output acknowledge pin connections implemented for csCTI in the debug system. The trigger input acknowledge signals are not connected to pins.

Table 84.  csCTI Trigger Input SignalsThe following table lists the trigger input pin connections implemented for csCTI.

Pin Number

Signal

Source

7

ASYNCOUT

STM

6

TRIGOUTHETE

STM

5

TRIGOUTSW

STM

4

TRIGOUTSPTE

STM

3

ACQCOMP

ETR

2

FULL

ETR

1

ACQCOMP

ETF

0

FULL

ETF

Table 85.  csCTI Trigger Output SignalsThe following table lists the trigger output pin connections implemented for csCTI.

Pin Number

Signal

Destination

7

TRIGIN

ETF

6

FLUSHIN

ETF

5

HWEVENTS[3:2]

STM

4

HWEVENTS[1:0]

STM

3

TRIGIN

TPIU

2

FLUSHIN

TPIU

1

TRIGIN

ETR

0

FLUSHIN

ETR

Table 86.  csCTI Trigger Output Acknowledge SignalsThe following table lists the trigger output pin acknowledge connections implemented for csCTI.

Pin Number

Signal

Source

7

0

6

0

5

0

4

0

3

TRIGINACK

TPIU

2

FLUSHINACK

TPIU

1

0

0

0