Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

2.2.8.4. UARTs

The HPS provides two UART controllers to provide asynchronous serial communications. The two UART modules are based on Synopsys* DesignWare* APB* Universal Asynchronous Receiver/ Transmitter peripheral and offer the following features:

  • 16550-compatible UART
  • Support automatic flow control as specified in 16750 standard
  • Programmable baud rate up to 6.25 MBaud (with 100MHz reference clock)
  • Direct access for host processor
  • DMA controller may be used for large transfers
  • 128-byte transmit and receive FIFO buffers