Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

20.4.3.4. EEPROM Read

Note: This transfer mode is only valid for serial masters.  †

When TMOD = 3, the transmit data is used to transmit an opcode, an address, or both to the EEPROM device. This takes three data frames (8‑bit opcode followed by 8‑bit upper address and 8‑bit lower address). During the transmission of the opcode and address, no data is captured by the receive logic (as long as the SPI master is transmitting data on its txd line, data on the rxd line is ignored). The SPI master continues to transmit data until the transmit FIFO buffer is empty. You should ONLY have enough data frames in the transmit FIFO buffer to supply the opcode and address to the EEPROM. If more data frames are in the transmit FIFO buffer than are needed, then Read data is lost.

When the transmit FIFO buffer becomes empty (all control information has been sent), data on the receive line (rxd) is valid and is stored in the receive FIFO buffer; the txd output is held at a constant logic level. The serial transfer continues until the number of data frames received by the SPI master matches the value of the NDF field in the CTRLR1 register plus one. †
Note: EEPROM read mode is not supported when the SPI controller is configured to be in the SSP mode. †