Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.3.6. Preload Engine

The preload engine (PLE) is a hardware block that enables the L2 cache to preload selected regions of memory.

The PLE signals the L2 cache when a cache line is needed in the L2 cache, by making the processor data master port start fetching the data. The processor data master does not complete the fetch or return the data to the processor. However, the L2 cache can then proceed to load the cache line. The data is only loaded to the L2 cache, not to the L1 cache or processor registers.

The preload functionality is under software control. The following PLE control parameters must be programmed:

  • Programmed parameters, including the following:
    • Base address
    • Length of stride
    • Number of blocks
  • A valid bit
  • TrustZone* memory protection for the cache memory, with an NS (non‑secure) state bit
  • A translation table base (TTB) address
  • An Address Space Identifier (ASID) value