Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

3.2.1. L4 Peripheral Clocks

The L4 peripheral clocks, denoted by l4_mp_clk, range up to 200 MHz.

Table 5.  Clock List
Peripheral Clock Name Description
USB OTG 0/16 hclk AHB* clock
pmu_hclk PMU AHB* clock. pmu_hclk is the scan clock for the PMU's AHB* domain.
Note: Select it as a test clock.
utmi_clk Always used as the PHY domain clock during DFT Scan mode.
Note: Select utmi_clk as a test clock even when the core is configured for a non-UTMI PHY.
Quad SPI Flash Controller6 pclk APB* clock
hclk AHB* clock
NAND Flash Controller (Locally gated nand_mp_clk.)6 ACLK AHB* Data port clock
mACLK AXI* Master port clock
regACLK AHB* Register port clock
ecc_clk ECC circuitry clock
clk_x Bus Interface Clock
EMAC 0/1 aclk Application clock for DMA AXI* bus and CSR APB* bus.
SD/MMC Controller sdmmc_clk All registers reside in the BIU clock domain.

For more information about the specific peripheral clocks, refer to their respective chapters.

6 Clock manager provides CSR bits for software enables to some peripherals. These enables are defaulted to enable. In boot mode, these enables are automatically active to ensure all clocks are active if RAM is cleared for security.