Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

9.3.4.1. Lightweight HPS-to-FPGA Bridge Master Signals

All the lightweight HPS-to-FPGA bridge master signals have a fixed width.

The following tables list all the signals exposed by the lightweight HPS-to-FPGA master interface to the FPGA fabric.

Table 51.  Lightweight HPS-to-FPGA Bridge Master Write Address Channel Signals
Signal Width Direction Description
AWID

12 bits

Output

Write address ID

AWADDR

21 bits

Output

Write address

AWLEN

4 bits

Output

Burst length

AWSIZE

3 bits

Output

Burst size

AWBURST

2 bits

Output

Burst type

AWLOCK

2 bits

Output

Lock type—Valid values are 00 (normal access) and 01 (exclusive access)

AWCACHE

4 bits

Output

Cache policy type

AWPROT

3 bits

Output

Protection type

AWVALID

1 bit

Output

Write address channel valid

AWREADY

1 bit

Input

Write address channel ready

Table 52.  Lightweight HPS-to-FPGA Bridge Master Write Data Channel Signals
Signal Width Direction Description
WID

12 bits

Output

Write ID

WDATA

32 bits

Output

Write data

WSTRB

4 bits

Output

Write data strobes

WLAST

1 bit

Output

Write last data identifier

WVALID

1 bit

Output

Write data channel valid

WREADY

1 bit

Input

Write data channel ready

Table 53.  Lightweight HPS-to-FPGA Bridge Master Write Response Channel Signals
Signal Width Direction Description
BID

12 bits

Input

Write response ID

BRESP

2 bits

Input

Write response

BVALID

1 bit

Input

Write response channel valid

BREADY

1 bit

Output

Write response channel ready

Table 54.  Lightweight HPS-to-FPGA Bridge Master Read Address Channel Signals
Signal Width Direction Description
ARID

12 bits

Output

Read address ID

ARADDR

21 bits

Output

Read address

ARLEN

4 bits

Output

Burst length

ARSIZE

3 bits

Output

Burst size

ARBURST

2 bits

Output

Burst type

ARLOCK

2 bits

Output

Lock type—Valid values are 00 (normal access) and 01 (exclusive access)

ARCACHE

4 bits

Output

Cache policy type

ARPROT

3 bits

Output

Protection type

ARVALID

1 bit

Output

Read address channel valid

ARREADY

1 bit

Input

Read address channel ready

Table 55.  Lightweight HPS-to-FPGA Bridge Master Read Data Channel Signals
Signal Width Direction Description
RID

12 bits

Input

Read ID

RDATA

32 bits

Input

Read data

RRESP

2 bits

Input

Read response

RLAST

1 bit

Input

Read last data identifier

RVALID

1 bit

Input

Read data channel valid

RREADY

1 bit

Output

Read data channel ready